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LVDS Buffer Internal Termination

ADS5547

SLWS192 – NOVEMBER 2006

Table 12. LVDS Buffer Currents Programming

DESCRIPTION

<LVDS CURRENT> – Output data and clock buffers current programmability

3.5 mA Default after reset

2.5 mA

4.5 mA

1.75 mA

<CURRENT DOUBLE> – The output data and clock buffer currents are doubled from the value selected by the <LVDS CURRENT>

Value specified by <LVDS

CURRENT>Default after reset

2x data, 2x clock currents

1x data, 2x clock currents

2x data, 4x clock currents

An internal termination option is available (using the serial interface), by which the LVDS buffers are differentially

terminated inside the device. The termination resistances available are – 325, 200, and 170

Ω (nominal with

±20% variation). Any combination of these three terminations can be programmed; the effective termination is

the parallel combination of the selected resistances. This results in eight effective terminations from open (no

termination) to 75

Ω.

The internal termination helps to absorb any reflections coming from the receiver end, improving the signal

integrity. With 100-

Ω internal and 100-Ω external termination, the voltage swing at the receiver end is halved

(compared to no internal termination). The voltage swing can be restored by using the LVDS current double

mode (see Table 12). Figure 47 shows the eye diagram of one of the LVDS data outputs with a 10-pF load

capacitance (from each pin to ground) and 100-

Ω internal termination enabled.

Figure 47. Eye Diagram of LVDS Data Output With Internal Termination

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