ADS5547 datasheet(33/50 Pages) TI

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Full−scale differential input pp + (Voltage forced on VCM)

1.33

(2)

Low Sampling Frequency Operation

Clock Input

CLKP

VCM

5kW

CLKM

VCM

ADS5547

SLWS192 – NOVEMBER 2006

APPLICATION INFORMATION (continued)

In this mode, the 1.5 V common-mode voltage to bias the input pins has to be generated externally. There is no

change in performance compared to internal reference mode.

For best performance at high sampling frequencies, ADS5547 uses a clock generator circuit to derive internal

timing for the ADC. The clock generator operates from 210 MSPS down to 50 MSPS in the DEFAULT SPEED

mode. The ADC enters this mode after applying reset (with serial interface configuration) or by tying SCLK pin to

low (with parallel configuration).

For low sampling frequencies (below 50 MSPS), the ADC must be put in the LOW SPEED mode. This mode

can be entered by:

• setting the register bit <LOW SPEED> through the serial interface, OR

• tying the SCLK pin to high (see Table 3) using the parallel configuration.

ADS5547 clock inputs can be driven differentially (SINE, LVPECL or LVDS) or single-ended (LVCMOS), with

little or no difference in performance between configurations. The common-mode voltage of the clock inputs is

set to VCM using internal 5-k

Ω resistors as shown in Figure 42. This allows the use of transformer-coupled drive

circuits for sine wave clock, or ac-coupling for LVPECL, LVDS clock sources (Figure 43 and Figure 44)

Figure 42. Internal Clock Buffer

For best performance, it is recommended to drive the clock inputs differentially, reducing susceptibility to

common-mode noise. In this case, it is best to connect both clock inputs to the differential input clock signal with

0.1-

µF capacitors, as shown in Figure 43.

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ADS5547 Datasheet(PDF) 33 Page - Texas Instruments