 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ADS5547 Datasheet(PDF) 40 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
ADS5547 Datasheet(HTML) 40 Page - Texas Instruments |
|
|
40 / 50 page  www.ti.com Parallel CMOS Output Clock Position Programmability ADS5547 SLWS192 – NOVEMBER 2006 Table 13. Programming Internal Termination for LVDS Data and Clock REGISTER ADDRESS REGISTER DATA DESCRIPTION A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 <DATA TERM> Internal termination - Option to terminate the LVDS DATA buffers inside the ADC to improve signal integrity. By default, internal termination is disabled. 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 No termination Default after reset 0 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 325 Ω 0 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 200 Ω 0 1 1 1 1 1 1 0 0 1 1 0 0 0 0 0 125 Ω 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 170 Ω 0 1 1 1 1 1 1 0 1 0 1 0 0 0 0 0 120 Ω 0 1 1 1 1 1 1 0 1 1 0 0 0 0 0 0 100 Ω 0 1 1 1 1 1 1 0 1 1 1 0 0 0 0 0 75 Ω <CLK TERM> Internal termination – Option to terminate the LVDS CLK buffers inside the ADC to improve signal integrity. By default, internal termination is disabled. 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 No termination Default after reset 0 1 1 1 1 1 1 0 0 0 0 0 0 1 0 0 325 Ω 0 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 200 Ω 0 1 1 1 1 1 1 0 0 0 0 0 1 1 0 0 125 Ω 0 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 170 Ω 0 1 1 1 1 1 1 0 0 0 0 1 0 1 0 0 120 Ω 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 100 Ω 0 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 75 Ω In this mode, the 14 data outputs and the output clock are available as 3.3-V CMOS voltage levels. Each data bit and the output clock is available on a separate pin in parallel. By default, the data outputs are valid during the rising edge of the output clock. The output clock is CLKOUT (pin 5). In both the LVDS and CMOS modes, the output clock can be moved around its default position. This can be done using SEN pin 27 (as described in Table 5) or using the serial interface register bits <CLKOUT POSN>. Using this allows to trade-off the setup and hold times leading to reliable data capture. There also exists an option to align the output clock edge with the data transition. Note that programming the output clock position also affects the clock propagation delay times. Table 14. CLKOUT Position Programing REGISTER ADDRESS REGISTER DATA DESCRIPTION A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 <CLKOUT POSN CMOS> – Output clock rising edge programmability in CMOS mode 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 Default position 0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 1 Output clock rising edge later by (1/12)Ts 0 1 1 0 0 0 1 0 0 0 0 0 0 1 0 1 Output clock rising edge later by (3/12)Ts 0 1 1 0 0 0 1 0 0 0 0 0 0 1 1 1 Output clock rising edge later by (2/12)Ts <CLKOUT POSN CMOS> – Output clock falling edge programmability in CMOS mode 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 Default position 0 1 1 0 0 0 1 0 0 0 0 0 1 0 0 1 Output clock falling edge later by (1/12)Ts 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 1 Output clock falling edge later by (3/12)Ts 0 1 1 0 0 0 1 0 0 0 0 1 1 0 0 1 Output clock falling edge later by (2/12)Ts 40 Submit Documentation Feedback |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
