LM5155 datasheet(17/51 Pages) TI

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9.3.5 Clock Synchronization (UVLO/SYNC Pin)

The switching frequency of the device can be synchronized to an external clock by pulling down the UVLO/

SYNC pin. The internal clock of the device is synchronized at the falling edge, but ignores the falling edge input

during the forced off-time which is determined by the maximum duty cycle limit. The external synchronization

clock must pull down the UVLO/SYNC pin voltage below 1.45 V (typical). The duty cycle of the pulldown pulse is

not limited, but the minimum pulldown pulse width must be greater than 150 ns, and the minimum pullup pulse

width must be greater than 250 ns. Figure 9-10 shows an implementation of the remote shutdown function. The

UVLO pin can be pulled down by a discrete MOSFET or an open-drain output of an MCU. In this configuration,

the device stops switching immediately after the UVLO pin is grounded, and the device shuts down 35 µs

(typical) after the UVLO pin is grounded.

UVLO/SYNC

SUPPLY

MCU

SHUTDOWN

Figure 9-10. UVLO and Shutdown

Figure 9-11 shows an implementation of shutdown and clock synchronization functions together. In this

configuration, the device stops switching immediately when the UVLO pin is grounded, and the device shuts

down if the fSYNC stays in high logic state for longer than 35 µs (typical) (UVLO is in low logic state for more than

35 µs (typical)). The device runs at fSYNC if clock pulses are provided after the device is enabled.

UVLO/SYNC

SUPPLY

MCU

SYNC

Figure 9-11. UVLO, Shutdown, and Clock Synchronization

Figure 9-13 and Figure 9-14 show implementations of standby and clock synchronization functions together. In

this configuration, the device stops switching immediately if fSYNC stays in high logic state and enters standby

mode if fSYNC stays in high logic state for longer than two switching cycles. The device runs at the fSYNC if clock

pulses are provided. Because the device can be enabled when the UVLO pin voltage is greater than the enable

threshold for more than 1.5 µs, the configurations in Figure 9-13 and Figure 9-14 are recommended if the

external clock synchronization pulses are provided from the start before the device is enabled. This 1.5-µs

requirement can be relaxed when the duty cycle of the synchronization pulse is greater than 50%. Figure 9-12

shows the required minimum duty cycle to start up by synchronization pulses. When the switching frequency is

greater than 1.1 MHz, the UVLO pin voltage should be greater than the enable threshold for more than 1.5 µs

before applying the external synchronization pulse.

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LM5155-Q1, LM51551-Q1

SNVSAY4E – AUGUST 2018 – REVISED JANUARY 2021

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LM5155 Datasheet(PDF) 17 Page - Texas Instruments