LM5155 datasheet(21/51 Pages) TI

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where

• VF is a forward voltage drop of D1, the external diode.

The recommended value for margin to cover non-ideal factors is 1.2. If required, RSL can be added to further

increase the slope of the compensation ramp. Typically 82% of the sensed inductor current falling slope is known

as an optimal amount of the slope compensation. The RSL value to achieve 82% of the sensed inductor current

falling slope is calculated as shown in Equation 9.

LOAD

SUPPLY

0.82

30uA

40mV

(9)

If clock synchronization is not used, the fSW frequency equals the fRT frequency. If clock synchronization is used,

the fSW frequency equals the fSYNC frequency. The maximum value for the RSL resistance is 2 kΩ.

9.3.7 Current Limit and Minimum On-time (CS Pin)

The device provides cycle-by-cycle peak current limit protection that turns off the MOSFET when the sum of the

inductor current and the programmable slope compensation ramp reaches the current limit threshold (VCLTH).

Peak inductor current limit (IPEAK-CL) in steady state is calculated as shown in Equation 10.

CLTH

SYNC

PEAK CL

30 A

P u

(10)

The practical duty cycle is greater than the estimated due to voltage drops across the MOSFET and sense

resistor. The estimated duty cycle is calculated as shown in Equation 11.

SUPPLY

LOAD

(11)

Boost converters have a natural pass-through path from the supply to the load through the high-side power

diode (D1). Because of this path and the minimum on-time limitation of the device, boost converters cannot

provide current limit protection when the output voltage is close to or less than the input supply voltage. The

minimum on-time is shown in Figure 8-12 and is calculated as Equation 12.

ON(MIN)

800 10

4 10

8 R

(12)

If required, a small external RC filter (RF, CF) at the CS pin can be added to overcome the large leading edge

spike of the current sense signal. Select an RF value in the range of 10 Ω to 200 Ω and a CF value in the range

of 100 pF to 2 nF. Because of the effect of this RC filter, the peak current limit is not valid when the on-time is

less than 2 × RF × CF. To fully discharge the CF during the off-time, the RC time constant should satisfy the

following inequality.

1 D

(13)

9.3.8 Feedback and Error Amplifier (FB, COMP Pin)

The feedback resistor divider is connected to an internal transconductance error amplifier which features high

output resistance (RO = 10 MΩ) and wide bandwidth (BW = 7 MHz). The internal transconductance error

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LM5155-Q1, LM51551-Q1

SNVSAY4E – AUGUST 2018 – REVISED JANUARY 2021

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