LM5155 datasheet(19/51 Pages) TI

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UVLO/SYNC

MCU

SYNC

Figure 9-15. Shutdown and Clock Synchronization

Figure 9-16 shows an implementation of inverted enable using external circuit.

UVLO/SYNC

SUPPLY

LMV431

Figure 9-16. Inverted UVLO

The external clock frequency (fSYNC) must be within +25% and –30% of fRT(TYPICAL). Because the maximum duty

cycle limit and the peak current limit with slope resistor (RSL) are affected by the clock synchronization, take

extra care when using the clock synchronization function. See Section 9.3.6, Section 9.3.7, and Section 9.3.11

for more information.

9.3.6 Current Sense and Slope Compensation (CS Pin)

The device has a low-side current sense and provides both fixed and optional programmable slope

compensation ramps, which help to prevent subharmonic oscillation at high duty cycle. Both fixed and

programmable slope compensation ramps are added to the sensed inductor current input for the PWM

operation, but only the programmable slope compensation ramp is added to the sensed inductor current input

(see Figure 9-17). For an accurate peak current limit operation over the input supply voltage, TI recommends

using only the fixed slope compensation (see Figure 8-5).

The device can generate the programmable slope compensation ramp using an external slope resistor (RSL) and

a sawtooth current source with a slope of 30 μA × fRT. This current flows out of the CS pin.

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LM5155-Q1, LM51551-Q1

SNVSAY4E – AUGUST 2018 – REVISED JANUARY 2021

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LM5155 Datasheet(PDF) 19 Page - Texas Instruments