LM5155 datasheet(23/51 Pages) TI

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9.3.11 Maximum Duty Cycle Limit and Minimum Input Supply Voltage

When designing boost converters, the maximum duty cycle should be reviewed at the minimum supply voltage.

The minimum input supply voltage that can achieve the target output voltage is limited by the maximum duty

cycle limit, and it can be estimated as follows.

SUPPLY(MIN)

LOAD

MAX

SUPPLY(MAX)

DCR

SUPPLY(MAX)

DS(ON)

MAX

1 D

(15)

where

• ISUPPLY(MAX) = the maximum input current.

• RDCR = the DC resistance of the inductor.

• RDS(ON) = the on-resistance of the MOSFET.

SYNC

MAX1

0.1

(16)

MAX2

1 100ns

(17)

The minimum input supply voltage can be further decreased by supplying fSYNC which is less than fRT. DMAX is

DMAX1 or DMAX2, whichever is lower.

9.3.12 MOSFET Driver (GATE Pin)

The device provides an N-channel MOSFET driver that can source or sink a peak current of 1.5 A. The peak

sourcing current is larger when supplying an external VCC that is higher than the 6.75-V VCC regulation target.

During start-up, especially when the input voltage range is below the VCC regulation target, the VCC voltage

must be sufficient to completely enhance the MOSFET. If the MOSFET drive voltage is lower than the MOSFET

gate plateau voltage during start-up, the boost converter may not start up properly and it can stick at the

maximum duty cycle in a high power dissipation state. This condition can be avoided by selecting a lower

threshold N-channel MOSFET switch and setting the VSUPPLY(ON) greater than 6 to 7 V. Since the internal VCC

regulator has a limited sourcing capability, the MOSFET gate charge should satisfy the following inequality.

G @ VCC

35mA

(18)

An internal 1-MΩ resistor is connected between GATE and PGND to prevent a false turnon during shutdown. In

boost topology, a switch node dV/dT must be limited during the 65-µs internal start-up delay to avoid a false

turnon, which is caused by the coupling through CDG parasitic capacitance of the MOSFET.

9.3.13 Overvoltage Protection (OVP)

The device has OVP for the output voltage. OVP is sensed at the FB pin. If the voltage at the FB pin rises above

the overvoltage threshold (VOVTH), OVP is triggered and switching stops. During OVP, the internal error amplifier

is operational, but the maximum source and sink capability is decreased to 40 µA.

9.3.14 Thermal Shutdown (TSD)

An internal thermal shutdown turns off the VCC regulator, disables switching, and pulls down the SS when the

junction temperature exceeds the thermal shutdown threshold (TTSD). After the temperature is decreased by

15°C, the VCC regulator is enabled again and the device performs a soft start.

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LM5155-Q1, LM51551-Q1

SNVSAY4E – AUGUST 2018 – REVISED JANUARY 2021

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