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STATUS

IICError RAIL error NVERRLOG

RegisterStatus

rc-0

r-0

IICError

Meaning

NoI2CPHY layererror

I2CPHY layererror

RAIL Error

Meaning

NoRAIL errorpending

RAIL errorpending

NVERRLOG

Meaning

ERRORpointstorun-timelogs

ERRORpointstonon-volatilelogs

Status

Meaning

NoError

Invalid Address

Read AccessError

Write AccessError

r-0

RAILSTATUS

rc-0

RAIL8

rc-0

RAIL7 RAIL6 RAIL5 RAIL4 RAIL3 RAIL2 RAIL1

RAILnMeaning

0=>No AlarmPendingforR

1=> AlarmPendingforRAILn

AIL

UCD9080

SLVS692A – SEPTEMBER 2006 – REVISED DECEMBER 2006

Error conditions encountered during processing will post error logs to this register. There are some exceptions.

This register is internally managed as a FIFO where errors are posted to the FIFO as they occur and read out of

the FIFO via I2C accesses. The FIFO is only posted to by the UCD9080 if it has room to write, due to the

unknown latency of the system reading out of this FIFO. Note that there is no real-time impact to the processing

of the UCD9080 if this FIFO is full and cannot be posted to.

The device time is reset by the following conditions:

1. Device Reset

2. A restart command issued to the device by the host via I2C.

3. A Resequence action is taken.

The STATUS is an 8-bit read-only register. This register provides real-time status information about the state of

the UCD9080. The following bits are defined.

Reading of the STATUS register clears the register except for the NVERRLOG bit, which is maintained until the

device is reset. Descriptions of the different errors are below.

The IICERROR bit is set when an I2C access fails. This is most often a case where the user has accessed an

invalid address, or performed an illegal number of operations for a given register (for example, reading 3 bytes

of a 2-byte register). In the event of an I2C error when the I2CERROR is set, bits 1:0 of the STATUS register

further define the nature of the error as shown above.

The RAIL error bit is set to alert the user to an issue with one of the voltage rails. When this bit is set, the user is

advised to then query the RAILSTATUS register to further ascertain which RAIL input(s) have an issue. The

user may then query the ERROR<n> registers to get further information about the nature of the error condition.

The NVERRLOG bit is set to 1 upon device initialization if the UCD9080 was restarted from a shutdown

sequence of a RAIL declared as critical. The purpose of this bit is to allow the user to differentiate between

stored error logs and real time error logs, and is useful for a post-mortem debug. Note that this bit is the only bit

that is not automatically cleared by a read of the STATUS register; this bit is only cleared at device reset if the

non-volatile error logs are empty.

When the IICERROR bit is set, the Register Status bits provide further information about the type of I2C error

that has been detected, as indicated above.

The RAILSTATUS1 and RAILSTATUS2 registers are two 8-bit read-only registers that provide a bit-mask that

represent the error status of the rails as indicated in the diagram below.

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