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FLASHLOCK

FLASHLOCK

7

6

5

4

3

2

1

0

rw-0

rw-0

rw-0

rw-0

rw-0

rw-0

rw-0

rw-0

FLASHLOCK

0x00

FLASHislocked(default)

0x01

FLASHisbeingupdated

0x02

Unlockflash(beforeconfiguration)

RESTART

WADDR and WDATA

Address

0

7

8

15

rw-0x00

rw-0x00

WADDR2

(0x31)

WADDR1

(0x30)

UCD9080

SLVS692A – SEPTEMBER 2006 – REVISED DECEMBER 2006

Bits 15:8 are RAILSTATUS1 and bits 7:0 are RAILSTATUS2. These are read as two 8-bit registers or as a

single 16-bit register.

If a bit is set in these registers, then the ERROR register is read to further ascertain the specific error. Bits in the

RAILSTATUS1 and RAILSTATUS2 registers are cleared when read.

updating the configuration. The section below (Configuring the UCD9080) details this process.

The format for the FLASHLOCK command is as follows:

UCD9080. This is an 8-bit register and when written to with a 0, the UCD9080 is restarted and the rails are

resequenced. This is useful for restarting the sequencer after the configuration for the system is changed. In

order to properly restart the system, this register must be written to a 0.

µs delay before the system is restarted,

map, WADDR and WDATA (see NOTE). Each of these registers are 8-bits and there are two of each (e.g.,

WADDR1, WADDR2 and WDATA1, WDATA2) to be able to write addresses and data of up to 16b.

NOTE:

In addition to updating the WADDR and WDATA commands, users can use the

FLASHLOCK command to perform configuration updates to the UCD9080.

The format for the WADDR command is as follows:

To set the address in the UCD9080 to write, write the LSB of the address to the WADDR1 register and the MSB

of the address to the WADDR2 register. For example, to write the address 0x1234 to the device, set WADDR1 =

0x34 and WADDR2 = 0x12. Note that since these addresses support the auto-increment feature, the user can

perform a single 16b write to WADDR1 to write the entire address.

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