3

Integrated

Circuit

Systems, Inc.

ICS954309

1044A—02/20/07

Pin Description (Continued)

PIN #

PIN NAME

PIN TYPE

DESCRIPTION

33

IREF

OUT

This pin establishes the reference current for the differential current-mode output

pairs. This pin requires a fixed precision resistor tied to ground in order to

establish the appropriate current. 475 ohms is the standard value.

34

CPUCLKC1

OUT

Complementary clock of differential pair CPU outputs. These are current mode

outputs. External resistors are required for voltage bias.

35

CPUCLKT1

OUT

True clock of differential pair CPU outputs. These are current mode outputs.

External resistors are required for voltage bias.

36

VDDCPU

PWR

Supply for CPU clocks, 3.3V nominal

37

GNDCPU

PWR

Ground pin for the CPU outputs

38

CPUCLKC0

OUT

Complementary clock of differential pair CPU outputs. These are current mode

outputs. External resistors are required for voltage bias.

39

CPUCLKT0

OUT

True clock of differential pair CPU outputs. These are current mode outputs.

External resistors are required for voltage bias.

40

CPU_STOP#

IN

Stops all CPUCLK, except those set to be free running clocks

41

SMBCLK

IN

Clock pin of SMBUS circuitry, 5V tolerant

42

SMBDAT

I/O

Data pin of SMBUS circuitry, 5V tolerant

43

VDDREF

PWR

Ref, XTAL power supply, nominal 3.3V

44

X2

OUT

Crystal output, Nominally 14.318MHz

45

X1

IN

Crystal input, Nominally 14.318MHz.

46

GNDREF

PWR

Ground pin for the REF outputs.

47

REF

OUT

14.318 MHz reference clock.

48

VDDPCI

PWR

Power supply for PCI clocks, nominal 3.3V

49

PCICLK3

OUT

PCI clock output.

50

PCICLK2

OUT

PCI clock output.

51

PCICLK1

OUT

PCI clock output.

52

PCICLK0

OUT

PCI clock output.

53

ITP_EN/PCICLK_F0

I/O

Free running PCI clock not affected by PCI_STOP#.

ITP_EN: latched input to select pin functionality

1 = CPU_ITP pair

0 = SRC pair

54

VDDPCI

PWR

Power supply for PCI clocks, nominal 3.3V

55

GNDPCI

PWR

Ground pin for the PCI outputs

56

VTT_PWRGD#/PD

IN

Vtt_PwrGd# is an active low input used to determine when latched inputs are

ready to be sampled. PD is an asynchronous active high input pin used to put the

device into a low power state. The internal clocks, PLLs and the crystal oscillator

are stopped.

57

FS_C/TEST_SEL

IN

3.3V tolerant input for CPU frequency selection. Low voltage threshold inputs,

see input electrical characteristics for Vil_FS and Vih_FS values.

TEST_Sel: 3-level latched input to enable test mode.

Refer to Test Clarification Table

58

USB_48MHZ/FS_A

I/O

Frequency select latch input pin / Fixed 48MHz USB clock output. 3.3V.

59

GNDPCI

PWR

Ground pin for the PCI outputs

60

VDD48

PWR

Power pin for the 48MHz output.3.3V

61

DOTT_96MHZ

OUT

True clock of differential pair for 96.00MHz DOT clock.

62

DOTC_96MHZ

OUT

Complement clock of differential pair for 96.00MHz DOT clock.

63

FS_B/TEST_MODE

IN

3.3V tolerant input for CPU frequency selection. Refer to input electrical

characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time input to

select between Hi-Z and REF/N divider mode while in test mode. Refer to Test

Clarification Table.

64

OE1#

IN

Active low input for enabling DIF pair 1.

1 = tri-state outputs, 0 = enable outputs

NOTE: Only OE# pins have internal pull-up resistors. No other inputs have pull-up or pull-down resistors.