6

Integrated

Circuit

Systems, Inc.

ICS954309

1044A—02/20/07

Absolute Max

Symbol

Parameter

Min

Max

Units

VDD_A

3.3V Core Supply Voltage

VDD + 0.5V

V

VDD_In

3.3V Logic Input Supply Voltage

GND - 0.5

VDD + 0.5V

V

Ts

Storage Temperature

-65

150

°C

Tambient

Ambient Operating Temp

0

70

°C

Tcase

Case Temperature

115

°C

ESD prot

Input ESD protection

human body model

2000

V

Electrical Characteristics - Input/Supply/Common Output Parameters

TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS Notes

Input High Voltage

VIH

3.3 V +/-5%

2

VDD + 0.3

V

1

Input Low Voltage

VIL

3.3 V +/-5%

VSS - 0.3

0.8

V

1

Input High Current

IIH

VIN = VDD

-5

5

uA

1

IIL1

VIN = 0 V; Inputs with no pull-

up resistors

-5

uA

1

IIL2

VIN = 0 V; Inputs with pull-up

resistors

-200

uA

1

Low Threshold Input-

High Voltage

VIH_FS

3.3 V +/-5%

0.7

VDD + 0.3

V

1

Low Threshold Input-

Low Voltage

VIL_FS

3.3 V +/-5%

VSS - 0.3

0.35

V

1

Operating Current

IDD3.3OP

All outputs driven, Full Active

500

mA

1

all diff pairs driven

70

mA

1

all differential pairs tri-stated

12

mA

1

Input Frequency

Fi

VDD = 3.3 V

14.31818

MHz

2

Pin Inductance

Lpin

7nH

1

CIN

Logic Inputs

5

pF

1

COUT

Output pin capacitance

6

pF

1

CINX

X1 & X2 pins

5

pF

1

Clk Stabilization

TSTAB

From VDD Power-Up or de-

assertion of PD to 1st clock

1.8

ms

1

Modulation Frequency

Triangular Modulation

30

32.540

33

kHz

1

Tdrive_PD

CPU output enable after

PD de-assertion

300

us

1

Tfall_PD

PD fall time of

5

ns

1

Trise_PD

PD rise time of

5

ns

1

Tdrive_CPU_STOP

CPU output enable after

CPU_STOP de-assertion

10

ns

1

Tfall_CPU_STOP

CPU_STOP fall time of

5

ns

1

Trise_CPU_STOP#

CPU_STOP rise time of

5

ns

1

SMBus Voltage

VDD

2.7

5.5

V

1

Low-level Output Voltage

VOL

@ IPULLUP

0.4

V

1

Current sinking at

VOL = 0.4 V

IPULLUP

4mA

1

SCLK/SDATA

Clock/Data Rise Time

TRI2C

(Max VIL - 0.15) to

(Min VIH + 0.15)

1000

ns

1

SCLK/SDATA

Clock/Data Fall Time

TFI2C

(Min VIH + 0.15) to

(Max VIL - 0.15)

300

ns

1

1Guaranteed by design and characterization, not 100% tested in production.

ppm frequency accuracy on PLL outputs.

2 Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz to meet

Input Low Current

Powerdown Current

IDD3.3PD

Input Capacitance