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ICS954309 Datasheet(PDF) 12 Page - Renesas Technology Corp

Part # ICS954309
Description  Programmable Timing Control Hub™ for Mobile P4™ Systems
PDF  19 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ICS954309 Datasheet(HTML) 12 Page - Renesas Technology Corp

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12
Integrated
Circuit
Systems, Inc.
ICS954309
1044A—02/20/07
SMBus Table: Output Enable Control Register
Pin #
Name
Control Function
Type
01
PWD
Bit 7
CPUCLK2_ITP/SRCCLK7 EN
Output Enable
RW
Disabled (Hi-Z)
Enabled
1
Bit 6
SRCCLK6 EN
Output Enable
RW
Disabled (Hi-Z)
Enabled
1
Bit 5
SRCCLK5 EN
Output Enable
RW
Disabled (Hi-Z)
Enabled
1
Bit 4
0
Bit 3
SRCCLK3 EN
Output Enable
RW
Disabled (Hi-Z)
Enabled
1
Bit 2
SRCCLK2 EN
Output Enable
RW
Disabled (Hi-Z)
Enabled
1
Bit 1
SRCCLK1 EN
Output Enable
RW
Disabled (Hi-Z)
Enabled
1
Bit 0
SRCCLK0 EN
Output Enable
RW
Disabled (Hi-Z)
Enabled
1
SMBus Table: Spreading and Output Enable Control Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
PCI_F0 EN
Output Enable
RW
Disabled
Enabled
1
Bit 6
DOT_96MHz EN
Output Enable
RW
Disabled (Hi-Z)
Enabled
1
Bit 5
USB_48MHz EN
Output Enable
RW
Disabled
Enabled
1
Bit 4
REFCLK EN
Output Enable
RW
Disabled
Enabled
1
Bit 3
1
Bit 2
CPUCLK1 EN
Output Enable
RW
Disabled (Hi-Z)
Enabled
1
Bit 1
CPUCLK0 EN
Output Enable
RW
Disabled (Hi-Z)
Enabled
1
Bit 0
SS_EN for CPU, SRC and PCI Outputs
Spread Spectrum Enable
RW
Spread Off
Spread On
0
SMBus Table: Output Enable Control Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
1
Bit 6
1
Bit 5
PCICLK3 EN
Output Enable
RW
Disabled
Enabled
1
Bit 4
PCICLK2 EN
Output Enable
RW
Disabled
Enabled
1
Bit 3
PCICLK1 EN
Output Enable
RW
Disabled
Enabled
1
Bit 2
PCICLK0 EN
Output Enable
RW
Disabled
Enabled
1
Bit 1
1
Bit 0
1
SMBus Table: SRC Output Enable Control Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
SRCCLK7 OEB# Select
Selects OEB# Control
RW
Not Controlled
Controlled
0
Bit 6
0
Bit 5
SRCCLK5 OEB# Select
Selects OEB# Control
RW
Not Controlled
Controlled
0
Bit 4
0
Bit 3
0
Bit 2
SRCCLK2 OEB# Select
Selects OEB# Control
RW
Not Controlled
Controlled
0
Bit 1
0
Bit 0
0
Note: Please refer to CPU and SRC Clock Control Truth Tables
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
-
Byte 1
Reserved
Byte 3
-
-
-
-
Byte 0
-
-
-
Byte 2
Reserved
Reserved



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