LOW SKEW, ÷1, ÷2

LVCMOS/LVTTL CLOCK GENERATOR

8701 DATA SHEET

8

REVISION F 1/21/15

POWER CONSIDERATIONS

For Power Dissipation, please refer to a separate Application

Note: Power Dissipation for LVCMOS Buffer.

Driver Termination

For LVCMOS Output Termination, please refer to a separate

Application Note: LVCMOS Driver Termination.

APPLICATION INFORMATION

INPUTS:

LVCMOS CONTROL PINS:

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional

protection. A 1k

Ω resistor can be used.

RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS

OUTPUTS:

LVCMOS OUTPUT:

All unused LVCMOS output can be left floating. We recommend

that there is no trace attached.