LOW SKEW, ÷1, ÷2

LVCMOS/LVTTL CLOCK GENERATOR

8701 DATA SHEET

2

REVISION F 1/21/15

TABLE 1. PIN DESCRIPTIONS

Number

Name

Type

Description

2, 5, 11,

26, 32, 35, 41,

44

V

DDO

Power

Output supply pins.

7, 9, 18, 21,

28, 30, 37, 39,

46, 48

GND

Power

Power supply ground.

16, 20

V

DD

Power

Positive supply pins.

25, 27, 29,

31, 33

QA0, QA1, QA2,

QA3, QA4

Output

Bank A outputs.LVCMOS / LVTTLinterface levels.

7

Ω typical output impedance.

34, 36, 38,

40, 42

QB0, QB1, QB2,

QB3, QB4

Output

Bank B outputs.LVCMOS / LVTTLinterface levels.

7

Ω typical output impedance.

43, 45, 47,

1, 3

QC0, QC1, QC2,

QC3, QC4

Output

Bank C outputs.LVCMOS / LVTTLinterface levels.

7

Ω typical output impedance.

4, 6, 8,

10, 12

QD0, QD1, QD2,

QD3, QD4

Output

Bank D outputs. LVCMOS / LVTTLinterface levels.

7

Ω typical output impedance.

22

CLK

Input

Pulldown LVCMOS / LVTTL clock input.

13

DIV_SELD

Input

Pullup

Controls frequency division for Bank D outputs.

LVCMOS / LVTTLinterface levels.

14

DIV_SELC

Input

Pullup

Controls frequency division for Bank C outputs.

LVCMOS / LVTTLinterface levels.

23

DIV_SELB

Input

Pullup

Controls frequency division for Bank B outputs.

LVCMOS / LVTTLinterface levels.

24

DIV_SELA

Input

Pullup

Controls frequency division for Bank A outputs.

LVCMOS / LVTTLinterface levels.

17, 19

BANK_EN1,

BANK_EN0

Input

Pullup

Enables and disables outputs by banks.

LVCMOS / LVTTLinterface levels.

15

nMR/OE

Input

Pullup

Master Reset and output enable. When HIGH, output drivers are

enabled. Whe LOW, output drivers are in HiZ and dividers are reset.

LVCMOS / LVTTLinterface levels.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.