Low Skew, ÷1, ÷2

LVCMOS/LVTTL Clock Generator

8701

DATASHEET

8701 REVISION F JANUARY 21, 2015

1

©2015 Integrated Device Technology, Inc.

GENERAL DESCRIPTION

The 8701 is a low skew, ÷1, ÷2 LVCMOS/LVTTL Clock

Generator . The low impedance LVCMOS outputs are

designed to dr ive 50

Ω series orparallel terminated

transmission lines. The effective fanout can be increased from

20 to 40 by utilizing the ability of the outputs to drive two series

terminated lines.

The divide select inputs, DIV_SELx, control the output

frequency of each bank. The outputs can be utilized in

the ÷1, ÷2 or a combination of ÷1 and ÷2 modes. The

bank enable inputs, BANK_EN0:1, support enabling and

disabling each bank of outputs individually. The master

reset input, nMR/OE, resets the internal frequency dividers and

also controls the active and high impedance states of all outputs.

The 8701 is char acter iz ed at 3.3V and mix ed

3.3V input supply, and 2.5V output supply operating

modes. Guaranteed bank, output and part-to-part skew

characteristics make the 8701 ideal for those clock

distr ibution applications demanding w ell defined

performance and repeatability.

FEATURES

• Twenty LVCMOS outputs, 7

Ω typical output impedance

• One LVCMOS/LVTTL clock input

• Maximum output frequency: 250MHz

• Bank enable logic allows unused banks to be disabled

in reduced fanout applications

• Output skew: 250ps (maximum)

• Part-to-part skew: 600ps (maximum)

• Bank skew: 200ps (maximum)

• Multiple frequency skew: 300ps (maximum)

• 3.3V or mixed 3.3V input, 2.5V output operating

supply modes

• 0°C to 70°C ambient operating temperature

• Other divide values available on request

• Available in lead-free RoHS compliant package

BLOCK DIAGRAM

PIN ASSIGNMENT

48-Pin LQFP

7mm x 7mm x 1.4mm

Y Package

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