NXP Semiconductors

PCA9849

4-channel ultra-low voltage, Fm+ I2C-bus multiplexer with reset

6.3 Control register

Following the successful acknowledgement of the slave address, the bus master will send a byte to the

PCA9849, which will be stored in the control register. If multiple bytes are received by the PCA9849, it will save

the last byte received. This register can be written and read via the I2C-bus.

aaa-028906

X

X

X

X

X

B2 B1 B0

channel selection bits

(read/write)

7

6

5

4

3

2

1

0

enable bit

Figure 9. Control register

6.3.1 Control register definition

An SCx/SDx downstream pair, or channel, is selected by the contents of the control register. This register

is written after the PCA9849 has been addressed. All 8 bits of the control byte are used to determine which

channel or channels are to be selected. Only the two lower bits of the control register are used to determine

which channel is selected. When a channel is selected, it will become active after a STOP condition has been

placed on the I2C-bus. This ensures that all SCx/SDx lines will be in a HIGH state when the channel is made

active, so that no false conditions are generated at the time of connection. Notice that only a single channel may

be selected at any one time.

Write = channel selection; Read = channel status

B7

B6

B5

B4

B3

B2

B1

B0

Command

X

X

X

X

X

0

X

X

No channel selected

X

X

X

X

X

1

0

0

Channel 0 enabled

X

X

X

X

X

1

0

1

Channel 1 enabled

X

X

X

X

X

1

1

0

Channel 2 enabled

X

X

X

X

X

1

1

1

Channel 3 enabled

0

0

0

0

0

0

0

0

All channels disabled; power-up/reset

default state

Table 6. Control register

Remark: Since this device is a multiplexer, only a single channel may be enabled at any one time.

6.4 RESET input

The RESET input is an active LOW signal which may be used to recover from a bus fault condition. By

asserting this signal LOW for a minimum of tw(rst)L, the PCA9849 will reset its registers and I2C-bus state

machine and will deselect all channels.

6.5 Power-on reset

When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9849 in a reset condition until

VDD2 has reached VPOR. At this point, the reset condition is released and the PCA9849 registers and I2C-bus

state machine are initialized to their default states (all zeroes) causing all the channels to be deselected.

PCA9849

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Product data sheet

Rev. 2.0 — 30 June 2023

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