NXP Semiconductors

PCA9849

4-channel ultra-low voltage, Fm+ I2C-bus multiplexer with reset

Another point to examine is that there is no buffering capability between the upstream and the downstream

buses. This is simply a pass transistor, which acts like a switch and a series resistor, between these bus

segments. The series resistance is the Ron of the pass transistor and is inversely proportional to the minimum

of VDD1 + VTH or VDD2, where VTH is approximately 0.8 V. Refer to Table 9 for some representative Ron values.

An upcoming application note will explain Ron more thoroughly. Therefore, a careful analysis of bus capacitance

and pull-up resistor values is called for.

A further point to consider is pull-up resistor selection. When a downstream channel is selected, the resistors on

the upstream or master side and the resistors on the downstream or slave side are effectively in parallel. Ensure

each device can correctly drive the effiective pull-up resistor value and still meet the LOW-level specifications.

PCA9849

SC0

SD0

SDA

SCL

1.8 V

0.8 V

MICRO-

CONTROLLER

aaa-018029

SDA

SCL

SC1

SD1

SC2

SD2

VDD2

0.8 V

VDD1

3.3 V 3.3 V

1.8 V 1.8 V

2.5 V 2.5 V

SCL

SDA

TEMP

SENSOR

3.3 V

SCL

SDA

GPIO

1.8 V

SCL

SDA

POWER MGMT

CONTROLLER

2.5 V

VDD

0.8 V 0.8 V

SC3

SD3

0.8 V to 3.6 V

SCL

SDA

I2C-BUS

PERIPHERAL

0.8 V to 3.6 V

Figure 13. Typical application for PCA9849 with differing bus voltages

7 Characteristics of the I2C-bus

The PCA9849 is an I2C slave device. Data is exchanged between the master and the PCA9849 through write

and read commands conforming to the I2C-bus protocol. The two communication lines are SCL (serial clock)

and SDA (serial data), both of which must be connected to VDD1 through pull-up resistors.

7.1 Write commands

Data is transmitted to the PCA9849 by sending its device address and setting the Least Significant Bit (LSB)

to a logic 0 (see Table 5 for device addresses), which the PCA9849 acknowledges (ACK). The control register

byte is sent after the address that determines which downstream channel is connected to the upstream channel

by bit 0 through bit 2. Bit 7 through bit 3 are ignored and can be written with any data. There is no limit on the

number of bytes sent after the address and before a STOP condition, only the last byte written before the STOP

condition is recognized and the selected channel is enabled only at the following STOP condition.

PCA9849

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© 2023 NXP B.V. All rights reserved.

Product data sheet

Rev. 2.0 — 30 June 2023

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