NXP Semiconductors

PCA9849

4-channel ultra-low voltage, Fm+ I2C-bus multiplexer with reset

aaa-019449

B7 B6 B5 B4 B3 B2 B1 B0

1/0

1

1/0 1/0 1/0 1/0

0

A

S

1

A

P

slave address

START condition

R/W acknowledge

from slave

acknowledge

from slave

control register

SDA

STOP condition

Refer to Table 5.

Figure 14. Write control register

7.2 Read commands

Data is read from the PCA9849 by sending its device address and setting the Least Significant Bit (LSB) to a

logic 1 (see Table 5 for device addresses), which the PCA9849 acknowledges. The control register byte is read

by the master with each byte either ACK or NACK by the master. If the master ACKs the control register byte, it

continues to send register data until the master NACKs, signaling the transaction is complete. There is no limit

on the number of bytes read from the PCA9849.

The control register bit definitions are shown in Figure 9. Bit 0 through bit 2 will show the enabled channels (as

determined by the last write).

aaa-019450

B7 B6

B3 B2 B1 B0

1/0

1

1/0 1/0 1/0 1/0

1

A

S

1

NA

P

target address

START condition

R/W acknowledge

from target

no acknowledge

from controller

control register

SDA

STOP condition

last byte

B5 B4

Refer to Table 5.

Figure 15. Read control register

8 Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Voltages are referenced to VSS (ground = 0 V)[1].

Symbol

Parameter

Conditions

Min

Max

Unit

VDD

supply voltage

-0.5

+4.0

V

VI

input voltage

-0.5

+4.0

V

II

input current

-

±20

mA

IO

output current

-

±25

mA

IDD

supply current

-

±100

mA

ISS

ground supply current

-

±100

mA

Ptot

total power dissipation

-

400

mW

Tstg

storage temperature

-60

+150

°C

Tamb

ambient temperature

operating

-40

+85

°C

Table 8. Limiting values

PCA9849

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© 2023 NXP B.V. All rights reserved.

Product data sheet

Rev. 2.0 — 30 June 2023

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