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ST7789V2 Datasheet(PDF) 115 Page - Sitronix Technology Co., Ltd. |
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ST7789V2 Datasheet(HTML) 115 Page - Sitronix Technology Co., Ltd. |
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115 / 319 page ![]() ST7789V2 Version 1.0 Page 115 of 319 2016/11 Sitronix Confidential The information contained herein is the exclusive property of Sitronix and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Sitronix. 8.9.3 RGB Interface Definition The display operation via the RGB interface is synchronized with the VSYNC, HSYNC, and DOTCLK signals. The data can be written only within the specified area with low power consumption by using window address function. The back porch and front porch are used to set the RGB interface timing. Figure 24 DRAM Access Area by RGB Interface Please refer to the following table for the setting limitation of RGB interface signals. Parameter Symbol Min. Typ. Max. Unit Horizontal Sync. Width hpw 2 10 hpw+hbp=31 Clock Horizontal Sync. Back Porch hbp 4 10 Clock Horizontal Sync. Front Porch hfp 2 38 - Clock Vertical Sync. Width vs 2 4 vs+vbp=127 Line Vertical Sync. Back Porch vbp 2 4 Line Vertical Sync. Front Porch vfp 2 8 - Line Note: Typical value are related to the setting of dot clock is 7MHz and frame rate is 70Hz.. If the setting of hpw is 10 dot clocks and hbp is 10 dot clocks, the setting of HBP in command B1h is 20 dot clocks |
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