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ST7789V2 Datasheet(PDF) 217 Page - Sitronix Technology Co., Ltd. |
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ST7789V2 Datasheet(HTML) 217 Page - Sitronix Technology Co., Ltd. |
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217 / 319 page  ST7789V2 Version 1.0 Page 217 of 319 2016/11 Sitronix Confidential The information contained herein is the exclusive property of Sitronix and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Sitronix. 9.1.28 MADCTL (36h): Memory Data Access Control 36H MADCTL (Memory Data Access Control) Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX MADCTL 0 ↑ 1 - 0 0 1 1 0 1 1 0 (36h) parameter 1 ↑ 1 - MY MX MV ML RGB MH - - Description -This command defines read/ write scanning direction of frame memory. -Bit Assignment Bit D7- Page Address Order “0” = Top to Bottom (When MADCTL D7=”0”). “1” = Bottom to Top (When MADCTL D7=”1”). Bit D6- Column Address Order “0” = Left to Right (When MADCTL D6=”0”). “1” = Right to Left (When MADCTL D6=”1”). Bit D5- Page/Column Order “0” = Normal Mode (When MADCTL D5=”0”). “1” = Reverse Mode (When MADCTL D5=”1”) Note: Bits D7 to D5, alse refer to section 8.12 Address Control Bit D4- Line Address Order “0” = LCD Refresh Top to Bottom (When MADCTL D4=”0”) “1” = LCD Refresh Bottom to Top (When MADCTL D4=”1”) Bit D3- RGB/BGR Order “0” = RGB (When MADCTL D3=”0”) “1” = BGR (When MADCTL D3=”1”) Bit D2- Display Data Latch Data Order “0” = LCD Refresh Left to Right (When MADCTL D2=”0”) “1” = LCD Refresh Right to Left (When MADCTL D2=”1”) Bit NAME DESCRIPTION D7 MY Page Address Order D6 MX Column Address Order D5 MV Page/Column Order D4 ML Line Address Order D3 RGB RGB/BGR Order D2 MH Display Data Latch Order |
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