MC68340 datasheet(328/441 Pages) FREESCALE

328 / 441 page

MOTOROLA

MC68340 USER’S MANUAL

7- 33

DBB—Delta Break B

1 = The channel B receiver has detected the beginning or end of a received break.

0 = The CPU32 has issued a channel B reset break-change interrupt command.

Refer to 7.4.1.7 Command Register (CR) for more information on the reset

break-change interrupt command.

RxRDYB—Channel B Receiver Ready or FIFO Full

The function of this bit is programmed by MR1B bit 6.

1 = If programmed as receiver ready, a character has been received in channel B

and is waiting in the receiver buffer FIFO. If programmed as FIFO full, a

character has been transferred from the receiver shift register to the FIFO, and

the transfer has caused the channel B FIFO to become full (all three positions

are occupied).

0 = If programmed as receiver ready, the CPU32 has read the receiver buffer. After

this read, if more characters are still in the FIFO, the bit is set again after the

FIFO is 'popped'. If programmed as FIFO full, the CPU32 has read the receiver

buffer. If a character is waiting in the receiver shift register because the FIFO is

full, the bit will be set again when the waiting character is loaded into the FIFO.

TxRDYB—Channel B Transmitter Ready

This bit is the duplication of the TxRDY bit in SRB.

1 = The transmitter holding register is empty and ready to be loaded with a character.

This bit is set when the character is transferred to the transmitter shift register.

This bit is also set when the transmitter is first enabled. Characters loaded into

the transmitter holding register while the transmitter is disabled are not

transmitted.

0 = The transmitter holding register was loaded by the CPU32, or the transmitter is

disabled.

XTAL_RDY—Serial Clock Running

This bit is always read as a zero when the X1 clock is running. This bit cannot be

enabled to generate an interrupt.

1 = This bit is set at reset.

0 = This bit is cleared after the baud rate generator is stable. The CSR should not be

accessed until this bit is zero.

DBA—Delta Break A

1 = The channel A receiver has detected the beginning or end of a received break.

0 = The CPU32 has issued a channel A reset break-change interrupt command.

Refer to 7.4.1.7 Command Register (CR) for more information on the reset

break-change interrupt command.

Freescale Semiconductor, Inc.

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