MC68340 datasheet(329/441 Pages) FREESCALE

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7- 34

MC68340 USER’S MANUAL

MOTOROLA

RxRDYA—Channel A Receiver Ready or FIFO Full

The function of this bit is programmed by MR1A bit 6.

1 = If programmed as receiver ready, a character has been received in channel A

and is waiting in the receiver buffer FIFO. If programmed as FIFO full, a

character has been transferred from the receiver shift register to the FIFO, and

the transfer has caused the channel A FIFO to become full (all three positions

are occupied).

0 = If programmed as receiver ready, the CPU32 has read the receiver buffer. After

this read, if more characters are still in the FIFO, the bit is set again after the

FIFO is 'popped'. If programmed as FIFO full, the CPU32 has read the receiver

buffer. If a character is waiting in the receiver shift register because the FIFO is

full, the bit will be set again when the waiting character is loaded into the FIFO.

TxRDYA—Channel A Transmitter Ready

This bit is the duplication of the TxRDY bit in SRA.

1 = The transmitter holding register is empty and ready to be loaded with a character.

This bit is set when the character is transferred to the transmitter shift register.

This bit is also set when the transmitter is first enabled. Characters loaded into

the transmitter holding register while the transmitter is disabled are not

transmitted.

0 = The transmitter holding register was loaded by the CPU32, or the transmitter is

disabled.

7.4.1.13 INTERRUPT ENABLE REGISTER (IER). The IER selects the corresponding bits

in the ISR that cause an interrupt output (

IRQ

≈). If one of the bits in the ISR is set and the

corresponding bit in the IER is also set, the

IRQ

≈ output is asserted. If the corresponding

bit in the IER is zero, the state of the bit in the ISR has no effect on the

IRQ

≈ output. The

IER does not mask the reading of the ISR. The ISR XTAL_RDY bit cannot be enabled to

generate an interrupt. This register can only be written when the serial module is enabled

(i.e., the STP bit in the MCR is cleared).

IER

$715

76543210

COS

DBB

RxRDYB TxRDYB

DBA

RxRDYA TxRDYA

RESET:

00000000

Write Only

Supervisor/User

COS—Change-of-State

1 = Enable interrupt

0 = Disable interrupt

DBB—Delta Break B

1 = Enable interrupt

0 = Disable interrupt

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