ADUC7021 datasheet(49/92 Pages) AD

49 / 92 page

ADuC7019/20/21/22/24/25/26/27

Rev. A | Page 49 of 92

Linearity degradation near ground and VDD is caused by

saturation of the output amplifier, and a general representation

of its effects (neglecting offset and gain error) is illustrated in

Figure 52. The dotted line in Figure 52 indicates the ideal transfer

function, and the solid line represents what the transfer function

might look like with endpoint nonlinearities due to saturation of

the output amplifier. Note that Figure 52 represents a transfer

function in 0-to-AVDD mode only. In 0-to-VREF or 0-to-DACREF

modes (with VREF < AVDD or DACREF < AVDD), the lower non-

linearity is similar. However, the upper portion of the transfer

function follows the “ideal” line right to the end (VREF in this case,

not AVDD), showing no signs of endpoint linearity errors.

AVDD

AVDD – 100mV

100mV

0x00000000

0x0FFF0000

Figure 52. Endpoint Nonlinearities Due to Amplifier Saturation

The endpoint nonlinearities conceptually illustrated in

Figure 52 get worse as a function of output loading. Most of

the ADuC7019/7020/7021/7022/7024/7025/7026/7027’s data

sheet specifications assume a 5 kΩ resistive load to ground at

the DAC output. As the output is forced to source or sink more

current, the nonlinear regions at the top or bottom

(respectively) of Figure 52 become larger. With larger current

demands, this can significantly limit output voltage swing.

POWER SUPPLY MONITOR

The power supply monitor regulates the IOVDD supply on the

ADuC7019/7020/7021/7022/7024/7025/7026/7027. It indicates

when the IOVDD supply pin drops below one of two supply trip

points. The monitor function is controlled via the PSMCON

monitor interrupts the core using the PSMI bit in the PSMCON

MMR. This bit is immediately cleared once CMP goes high.

This monitor function allows the user to save working registers

to avoid possible data loss due to the low supply or brown-out

conditions. It also ensures that normal code execution does not

resume until a safe supply level has been established.

PSMCON Register

Name

Address

Default Value

Access

PSMCON

0xFFFF0440

0x0008

R/W

Table 28. PSMCON MMR Bit Descriptions

Bit

Name

Description

CMP

Comparator Bit. This is a read-only bit and

directly reflects the state of the comparator.

Read 1 indicates that the IOVDD supply is above

its selected trip point or the PSM is in power-

down mode. Read 0 indicates the IOVDD supply is

below its selected trip point. This bit should be

set before leaving the interrupt service routine.

Trip Point Selection Bits. 0 = 2.79 V, 1 = 3.07 V.

PSMEN

Power Supply Monitor Enable Bit. Set to 1 to

enable the power supply monitor circuit. Clear to

0 to disable the power supply monitor circuit.

PSMI

Power Supply Monitor Interrupt Bit. This bit is set

high by the MicroConverter once when CMP

goes low, indicating low I/O supply. The PSMI bit

can be used to interrupt the processor. Once

CMP returns high, the PSMI bit can be cleared by

writing a 1 to this location. A 0 write has no

effect. There is no timeout delay; PSMI can be

immediately cleared once CMP goes high.

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