ADUC7021 datasheet(18/92 Pages) AD

18 / 92 page

ADuC7019/20/21/22/24/25/26/27

Rev. A | Page 18 of 92

Table 10. Pin Function Descriptions (ADuC7019/ADuC7020/ADuC7021/ADuC7022)

Pin No.

7019/7020

7021

7022

Mnemonic

Description

ADC0

Single-Ended or Differential Analog Input 0.

ADC1

Single-Ended or Differential Analog Input 1.

ADC2/CMP0

Single-Ended or Differential Analog Input 2/Comparator Positive Input.

ADC3/CMP1

Single-Ended or Differential Analog Input 3 (Buffered Input on

ADuC7019)/Comparator Negative Input.

ADC4

Single-Ended or Differential Analog Input 4.

‒

ADC5

Single-Ended or Differential Analog Input 5.

‒

ADC6

Single-Ended or Differential Analog Input 6.

‒

ADC7

Single-Ended or Differential Analog Input 7.

‒

ADC8

Single-Ended or Differential Analog Input 8.

‒

ADC9

Single-Ended or Differential Analog Input 9.

GNDREF

Ground Voltage Reference for the ADC. For optimal performance, the

analog power supply should be separated from IOGND and DGND.

‒

DAC0/ADC12

DAC0 Voltage Output/Single-Ended or Differential Analog Input 12.

‒

DAC1/ADC13

DAC1 Voltage Output/Single-Ended or Differential Analog Input 13.

‒

DAC2/ADC14

DAC2 Voltage Output/Single-Ended or Differential Analog Input 14.

‒

DAC3/ADC15

DAC3 Voltage Output on ADuC7020. On the ADuC7019, a 10 nF capacitor

needs to be connected between this pin and AGND/Single-Ended or

Differential Analog Input 15.

TMS

Test Mode Select, JTAG Test Port Input. Debug and download access.

TDI

Test Data In, JTAG Test Port Input. Debug and download access.

BM/P0.0/CMPOUT/PLAI[7]

Multifunction I/O Pin.

Boot Mode (BM). The ADuC7019/20/21/22 enter serial download mode if

BM is low at reset and execute code if BM is pulled high at reset through a

1 k

Ω resistor. General-Purpose Input and Output Port 0.0/Voltage

Comparator Output/Programmable Logic Array Input Element 7.

P0.6/T1/MRST/PLAO[3]

Multifunction Pin, Driven Low After Reset. General-Purpose Output Port

0.6/Timer1 Input/Power-On Reset Output/Programmable Logic Array

Output Element 3.

TCK

Test Clock, JTAG Test Port Input. Debug and download access.

TDO

Test Data Out, JTAG Test Port Output. Debug and download access.

IOGND

Ground for GPIO. Typically connected to DGND.

IOVDD

3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator.

LVDD

2.6 V Output of the On-Chip Voltage Regulator. This output must be

connected to a 0.47 μf capacitor to DGND only.

DGND

Ground for Core Logic.

P0.3/TRST/ADCBUSY

General-Purpose Input and Output Port 0.3/Test Reset, JTAG Test Port

Input/ ADCBUSY Signal Output.

RST

Reset Input, Active Low.

IRQ0/P0.4/PWMTRIP/PLAO[1]

Multifunction I/O Pin. External Interrupt Request 0, Active High/General-

Purpose Input and Output Port 0.4/PWM Trip External

Input/Programmable Logic Array Output Element 1.

IRQ1/P0.5/ADCBUSY/PLAO[2]

Multifunction I/O Pin. External Interrupt Request 1, Active High/General-

Purpose Input andOutput Port 0.5/ADCBUSY Signa l Output/Programmable

Logic Array Output Element 2.

P2.0/SPM9/PLAO[5]/CONVSTART

Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/UART/

Programmable Logic Array Output Element 5/Start Conversion Input Signal

for ADC.

P0.7/ECLK/XCLK/SPM8/PLAO[4]

Serial Port Multiplexed. General-Purpose Input and Output Port

0.7/Output for External Clock Signal/Input to the Internal Clock Generator

Circuits/UART/ Programmable Logic Array Output Element 4.

XCLKO

Output from the Crystal Oscillator Inverter.

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