ADUC7021 datasheet(21/92 Pages) AD

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Table 11. Pin Function Descriptions (ADuC7024/ADuC7025 64-Lead CSP and ADuC7024/ADuC7025 64-Lead LQFP)

Pin No.

Mnemonic

Description

ADC4

Single-Ended or Differential Analog Input 4.

ADC5

Single-Ended or Differential Analog Input 5.

ADC6

Single-Ended or Differential Analog Input 6.

ADC7

Single-Ended or Differential Analog Input 7.

ADC8

Single-Ended or Differential Analog Input 8.

ADC9

Single-Ended or Differential Analog Input 9.

GNDREF

Ground Voltage Reference for the ADC. For optimal performance, the analog power supply

should be separated from IOGND and DGND.

ADCNEG

Bias Point or Negative Analog Input of the ADC in Pseudo Differential Mode. Must be connected

to the ground of the signal to convert. This bias point must be between 0 V and 1 V.

DAC0/ADC12

DAC0 Voltage Output/Single-Ended or Differential Analog Input 12. DAC outputs are not

present on the ADuC7025.

DAC1/ADC13

DAC1 Voltage Output/Single-Ended or Differential Analog Input 13. DAC outputs are not

present on the ADuC7025.

TMS

JTAG Test Port Input, Test Mode Select. Debug and download access.

TDI

JTAG Test Port Input, Test Data In. Debug and download access

P4.6/PLAO[14]

General-Purpose Input and Output Port 4.6/Programmable Logic Array Output Element 14.

P4.7/PLAO[15]

General-Purpose Input and Output Port 4.7/Programmable Logic Array Output Element 15.

BM/P0.0/CMPOUT/PLAI[7]

Multifunction I/O Pin. Boot mode. The ADuC7024/ADuC7025 enter download mode if BM is low at

reset and executes code if BM is pulled high at reset through a 1 k

Ω resistor/General-Purpose Input

and Output Port 0.0/Voltage Comparator Output/Programmable Logic Array Input Element 7.

P0.6/T1/MRST/PLAO[3]

Multifunction Pin, Driven Low After Reset. General-Purpose Output Port 0.6/Timer1

Input/Power-On Reset Output/Programmable Logic Array Output Element 3.

TCK

JTAG Test Port Input, Test Clock. Debug and download access.

TDO

JTAG Test Port Output, Test Data Out. Debug and download access.

IOGND

Ground for GPIO. Typically connected to DGND.

IOVDD

3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator.

LVDD

2.6 V Output of the On-Chip Voltage Regulator. This output must be connected to a 0.47 μF

capacitor to DGND only.

DGND

Ground for Core Logic.

P3.0/PWM0H/PLAI[8]

General-Purpose Input and Output Port 3.0/PWM Phase 0 High-Side Output/Programmable

Logic Array Input Element 8.

P3.1/PWM0L/PLAI[9]

General-Purpose Input and Output Port 3.1/PWM Phase 0 Low-Side Output/Programmable

Logic Array Input Element 9.

P3.2/PWM1H/PLAI[10]

General-Purpose Input and Output Port 3.2/PWM Phase 1 High-Side Output/Programmable

Logic Array Input Element 10.

P3.3/PWM1L/PLAI[11]

General-Purpose Input and Output Port 3.3/PWM Phase 1 Low-Side Output/Programmable

Logic Array Input Element 11.

P0.3/TRST/ADCBUSY

General-Purpose Input and Output Port 0.3/JTAG Test Port Input, Test Reset/ADCBUSY Signal

Output.

RST

Reset Input, Active Low.

P3.4/PWM2H/PLAI[12]

General-Purpose Input and Output Port 3.4/PWM Phase 2 High-Side Output/Programmable

Logic Array Input 12.

P3.5/PWM2L/PLAI[13]

General-Purpose Input and Output Port 3.5/PWM Phase 2 Low-Side Output/Programmable

Logic Array Input Element 13.

IRQ0/P0.4/PWMTRIP/PLAO[1]

Multifunction I/O Pin. External Interrupt Request 0, Active High/General-Purpose Input and

Output Port 0.4/PWM Trip External Input/Programmable Logic Array Output Element 1.

IRQ1/P0.5/ADCBUSY/PLAO[2]

Multifunction I/O Pin. External Interrupt Request 1, Active High/General-Purpose Input and

Output Port 0.5/ADCBUSY Signal Output/Programmable Logic Array Output Element 2.

P2.0/SPM9/PLAO[5]/CONVSTART

Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/UART/Programmable Logic

Array Output Element 5/Start Conversion Input Signal for ADC.

P0.7/ECLK/XCLK/SPM8/PLAO[4]

Serial Port Multiplexed. General-Purpose Input and Output Port 0.7/Output for External Clock

Signal/Input to the Internal Clock Generator Circuits/UART/Programmable Logic Array Output

Element 4.

XCLKO

Output from the Crystal Oscillator Inverter.

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