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ADUC7021 Datasheet(PDF) 13 Page - Analog Devices |
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ADUC7021 Datasheet(HTML) 13 Page - Analog Devices |
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13 / 92 page  ADuC7019/20/21/22/24/25/26/27 Rev. A | Page 13 of 92 Table 6. SPI Master Mode Timing (PHASE Mode = 0) Parameter Description Min Typ Max Unit tSL SCLOCK low pulse width1 (SPIDIV + 1) × tHCLK ns tSH SCLOCK high pulse width1 (SPIDIV + 1) × tHCLK ns tDAV Data output valid after SCLOCK edge 25 ns tDOSU Data output setup before SCLOCK edge 75 ns tDSU Data input setup time before SCLOCK edge2 1 × tUCLK ns tDHD Data input hold time after SCLOCK edge2 2 × tUCLK ns tDF Data output fall time 5 12.5 ns tDR Data output rise time 5 12.5 ns tSR SCLOCK rise time 5 12.5 ns tSF SCLOCK fall time 5 12.5 ns 1 tHCLK depends on the clock divider or CD bits in PLLCON MMR. tHCLK = tUCLK/2CD. 2 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. SCLOCK (POLARITY = 0) SCLOCK (POLARITY = 1) tSH tSL tSR tSF MOSI MSB BITS 6–1 LSB MISO MSB IN BITS 6–1 LSB IN tDR tDF tDAV tDOSU tDSU tDHD Figure 7. SPI Master Mode Timing (PHASE Mode = 0) |
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