P87LPC778 datasheet(20/79 Pages) PHILIPS

20 / 79 page

Philips Semiconductors

P87LPC778

CMOS single-chip 8-bit microcontroller

Product data

Rev. 01 — 31 March 2004

20 of 79

9397 750 12378

8.5.5

Comparator conﬁguration example

The code shown below is an example of initializing one comparator. Comparator 1 is

conﬁgured to use the CIN1A and CMPREF inputs, outputs the comparator result to

the CMP1 pin, and generates an interrupt when the comparator output changes.

CmpInit: b

mov

PT0AD,#30h

; Disable digital inputs on pins that are used

;

for analog functions: CIN1A, CMPREF.

anl

P0M2,#0cfh

; Disable digital outputs on pins that are used

orl

P0M1,#30h

;

for analog functions: CIN1A, CMPREF.

mov

CMP1,#24h

; Turn on comparator 1 and set up for:

;

- Positive input on CIN1A.

;

- Negative input from CMPREF pin.

;

- Output to CMP1 pin enabled.

call

delay10us

; The comparator has to start up for at

;

least 10 microseconds before use.

anl

CMP1,#0feh

; Clear comparator 1 interrupt flag.

setb

EC1

; Enable the comparator 1 interrupt. The

;

priority is left at the current value.

setb

; Enable the interrupt system (if needed).

ret

; Return to caller.

The interrupt routine used for the comparator must clear the interrupt ﬂag (CMF1 in

this case) before returning.

8.6 Pulse width modulator

The P87LPC778 contains four Pulse Width Modulated (PWM) channels which can

generate pulses of programmable length and interval.

The output for PWM0 is on P0.1, PWM1 on P1.6, PWM2 on P1.7 and PWM3 on

P0.0.

After chip reset the output of the each PWM channel is reﬂect by the setting of

UCFG1.5, PRHI, if set to a zero the outputs are low, if set to one the outputs are high.

In this case PRHI is set to zero, before the pin will reﬂect the state of the internal

PWM output a ‘1’ must be written to each port bit that serves as a PWM output.

A block diagram is shown in Figure 8.

The interval between successive outputs is controlled by a 10–bit down counter

which uses the internal microcontroller clock as its input.

When bit 3 in the UCFG1 register is a ‘1’ (6-clock mode) the microcontroller clock,

and therefore the PWM counter clock, has the same frequency as the clock source:

(2)

When bit 3 in the UCFG1 register is a ‘0’ (12-clock mode) the microcontroller and

PWM counter clocks operate at half the frequency of clock source:

(3)

CPWM

OSC

CPWM

OSC

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