P87LPC778 datasheet(31/79 Pages) PHILIPS

31 / 79 page

Philips Semiconductors

P87LPC778

CMOS single-chip 8-bit microcontroller

Product data

Rev. 01 — 31 March 2004

31 of 79

9397 750 12378

Values to be used in the CT1 and CT0 bits are shown in Table 30. To allow the

I2C-bus to run at the maximum rate for a particular oscillator frequency, compare the

actual oscillator rate to the fosc max column in the table. The value for CT1 and CT0 is

found in the ﬁrst line of the table where CPU clock max is greater than or equal to the

actual frequency. Table 30 also shows the machine cycle count for various settings of

CT1/CT0. This allows calculation of the actual minimum high and low times for SCL

as follows:

(5)

For instance, at an 8 MHz frequency, with CT1/CT0 set to 1 0, the minimum SCL high

and low times will be 5.25

µs. Table 30 also shows the Timer I timeout period (given

in machine cycles) for each CT1/CT0 combination. The timeout period varies

because of the way in which minimum SCL high and low times are measured. When

the I2C-bus interface is operating, Timer I is pre-loaded at every SCL transition with a

value dependent upon CT1/CT0. The pre-load value is chosen such that a minimum

SCL high or low time has elapsed when Timer I reaches a count of 008 (the actual

value pre-loaded into Timer I is 8 minus the machine cycle count).

Table 27:

I2CFG - I2C-bus conﬁguration register (address C8h) bit allocation

Not bit addressable; Reset value: 00H

Bit

Symbol

SLAVEN

MASTRQ

CLRTI

TIRUN

CT1

CT0

Table 28:

I2CFG - I2C-bus conﬁguration register (address C8h) bit description

Bit

Symbol

Description

SLAVEN

Slave Enable. Writing a ‘1’ this bit enables the slave functions of

the I2C-bus subsystem. If SLAVEN and MASTRQ are ‘0’, the

I2C-bus hardware is disabled. This bit is cleared to ‘0’ by reset and

by an I2C-bus time-out.

MASTRQ

Master Request. Writing a ‘1’ to this bit requests mastership of the

I2C-bus. If a transmission is in progress when this bit is changed

from ‘0’ to ‘1’, action is delayed until a stop condition is detected. A

start condition is sent and DRDY is set (thus making ATN = 1 and

generating an I2C-bus interrupt). When a master wishes to release

mastership status of the I2C-bus, it writes a ‘1’ to XSTP in I2CON.

MASTRQ is cleared by an I2C-bus time-out.

CLRTI

Writing a ‘1’ to this bit clears the Timer I overﬂow ﬂag. This bit

position always reads as a ‘0’.

TIRUN

Writing a ‘1’ to this bit lets Timer I run; a ‘0’ stops and clears it.

Together with SLAVEN, MASTRQ, and MASTER, this bit

determines operational modes as shown in Table 29.

3, 2

Reserved for future use. Should not be set to ‘1’ by user programs.

1, 0

CT1, CT0

These two bits are programmed as a function of the CPU clock

rate, to optimize the MIN HI and LO time of SCL when this device

is a master on the I2C-bus. The time value determined by these

bits controls both of these parameters, and also the timing for stop

and start conditions.

SCL min high/low time (in microseconds)

6 * min time count

CPUclock (in MHz)

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