P87LPC778 datasheet(30/79 Pages) PHILIPS

30 / 79 page

Philips Semiconductors

P87LPC778

CMOS single-chip 8-bit microcontroller

Product data

Rev. 01 — 31 March 2004

30 of 79

9397 750 12378

CSTP — Writing a ‘1’ to ‘Clear SToP’ clears the STP bit. Note that if one or more of

DRDY, ARL, STR, or STP is ‘1’, the low time of SCL is stretched until the service

routine responds by clearing them.

XSTR — Writing ‘1’s to ‘Xmit repeated STaRt’ and CDR tells the I2C-bus hardware to

send a repeated start condition. This should only be at a master. Note that XSTR

need not and should not be used to send an ‘initial’ (non-repeated) start; it is sent

automatically by the I2C-bus hardware. Writing XSTR = 1 includes the effect of writing

I2DAT with XDAT = 1; it sets Transmit Active and releases SDA to HIGH during the

SCL low time. After SCL goes HIGH, the I2C-bus hardware waits for the suitable

minimum time and then drives SDA low to make the start condition.

XSTP — Writing 1s to ‘Xmit SToP’ and CDR tells the I2C-bus hardware to send a stop

condition. This should only be done at a master. If there are no more messages to

initiate, the service routine should clear the MASTRQ bit in I2CFG to ‘0’ before writing

XSTP with ‘1’. Writing XSTP = 1 includes the effect of writing I2DAT with XDAT = 0; it

sets Transmit Active and drives SDA low during the SCL low time. After SCL goes

HIGH, the I2C-bus hardware waits for the suitable minimum time and then releases

SDA to HIGH to make the stop condition.

8.7.6

Regarding software response time

Because the P87LPC778 can run at 20 MHz, and because the I2C-bus interface is

optimized for high-speed operation, it is quite likely that an I2C-bus service routine will

sometimes respond to DRDY (which is set at a rising edge of SCL) and write I2DAT

before SCL has gone low again. If XDAT were applied directly to SDA, this situation

would produce an I2C-bus protocol violation. The programmer need not worry about

this possibility because XDAT is applied to SDA only when SCL is low.

Conversely, a program that includes an I2C-bus service routine may take a long time

to respond to DRDY. Typically, an I2C-bus routine operates on a ﬂag-polling basis

during a message, with interrupts from other peripheral functions enabled. If an

interrupt occurs, it will delay the response of the I2C-bus service routine. The

programmer need not worry about this very much either, because the I2C-bus

hardware stretches the SCL low time until the service routine responds. The only

constraint on the response is that it must not exceed the Timer I time-out.

Table 25:

I2DAT - I2C-bus data register (address D9H) bit allocation

Not bit addressable; Reset value: xxH

Bit

Symbol (R)

RDAT

-------

Symbol (W)

XDAT

-------

Table 26:

I2DAT - I2C-bus data register (address D9H) bit description

Bit

Symbol

Access

Description

RDAT

The most recently received data bit, captured from SDA at

every rising edge of SCL. Reading I2DAT also clears DRDY

and the Transmit Active state.

XDAT

Sets the data for the next transmitted bit. Writing I2DAT also

clears DRDY and sets the Transmit Active state.

6 to 0 -

Reserved for future use. Should not be set to ‘1’ by user

programs.

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