9397 750 12522

© Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Product data sheet

Rev. 01 — 13 October 2005

7 of 17

Philips Semiconductors

PCK9447

3.3 V/2.5 V 1 : 9 LVCMOS clock fan-out buffer

[1]

Dynamic characteristics apply for parallel output termination of 50

Ω to V

[2]

Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference

input pulse width, output duty cycle, and maximum frequency specifications. CCLK0, CCLK1; 0.7 V to 1.7 V.

[3]

Setup and hold times are referenced to the falling edge of the selected clock signal input.

[4]

Pulse skew time is the absolute difference of the propagation delay times:

| t

Table 9:

Dynamic characteristics (2.5 V)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

input frequency

0

-

350

MHz

output frequency

0

-

350

MHz

reference input pulse width

1.4

-

-

ns

propagation delay

CCLK0 or CCLK1 to any Q

1.7

-

4.4

ns

output disable time

-

-

11

ns

output enable time

-

-

11

ns

setup time

CCLK0 or CCLK1 to CLK_STOP

[3] 0.0

-

-

ns

hold time

CCLK0 or CCLK1 to CLK_STOP

[3] 1.0

-

-

ns

output skew time

output-to-output

-

-

150

ps

process skew time

part-to-part

-

-

2.7

ns

pulse skew time (output)

[4] -

-

200

ps

output duty cycle

45

50

55

%

output rise/fall time

0.6 V to 1.8 V

0.1

-

1.0

ns

Fig 3.

Output clock stop (CLK_STOP) timing diagram

CCLK0

or

CCLK1

CLK_STOP

Q0 to Q8

002aaa717

The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs.

Fig 4.

Cycle-to-cycle jitter time

002aab293