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© Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Product data sheet

Rev. 01 — 13 October 2005

10 of 17

Philips Semiconductors

PCK9447

3.3 V/2.5 V 1 : 9 LVCMOS clock fan-out buffer

At the load end the voltage will double, due to the near unity reflection coefficient, to 2.5 V.

It will then increment towards the quiescent 3.0 V in steps separated by one round trip

delay (in this case 4.0 ns).

Since this step is well above the threshold region it will not cause any false clock

triggering, however designers may be uncomfortable with unwanted reflections on the

line. To better match the impedances when driving multiple lines, the situation in Figure 13

should be used. In this case the series terminating resistors are reduced such that when

the parallel combination is added to the output buffer impedance the line impedance is

perfectly matched.

Fig 12. Single versus dual line termination waveforms

Fig 13. Optimized dual line termination

Z

O

50

Ω 50 Ω

R

S

33

Ω 33 Ω

R

O

17

Ω

=

||

=

||

=

V

L

3.0

25

16.5

17

25

++

-----------------------------------





1.28 V

=

=

time (ns)

014

12

48

002aaa679

3.0

voltage

(V)

−0.5

0

1.0

2.0

IN

OutA

OutB

Zo = 50 Ω

002aaa719

RS = 16 Ω

Zo = 50 Ω

RS = 16 Ω

PCK9447

OUTPUT

BUFFER

17

Ω

IN

Zo = 50 Ω

17

Ω 16 Ω 16 Ω

||

+

50

Ω 50 Ω

||

=

25

Ω

25

Ω

=