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PCK9447 Datasheet(PDF) 8 Page - NXP Semiconductors |
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PCK9447 Datasheet(HTML) 8 Page - NXP Semiconductors |
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8 / 17 page ![]() 9397 750 12522 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 13 October 2005 8 of 17 Philips Semiconductors PCK9447 3.3 V/2.5 V 1 : 9 LVCMOS clock fan-out buffer Fig 5. Propagation delay (tPD) test reference Fig 6. Pulse skew time (tsk(p)) test reference The pin-to-pin skew is defined as the worst-case difference in propagation delay between any similar delay path within a single device. The time from the output controlled edge to the non-controlled edge, divided by the time between output controlled edges, expressed as a percentage. Fig 7. Output skew time (tsk(o)) Fig 8. Output Duty Cycle ( δo) (1) 2.4 V (VCC = 3.3 V) 1.8 V (VCC = 2.5 V) (2) 0.55 V (VCC = 3.3 V) 0.6 V (VCC = 2.5 V) Fig 9. Output transition time test reference Fig 10. Setup and hold time (tsu, th) 002aab288 tPD CCLK Qn VCC VCC/2 GND VCC VCC/2 GND 002aab290 tPLH CCLK Qn VCC VCC/2 GND VCC VCC/2 GND tPHL tsk(p) = | tPLH − tPHL | 002aab289 tsk(o) VCC VCC/2 GND VCC VCC/2 GND tsk(o) 002aab291 tP VCC VCC/2 GND T0 δ = (tP ÷ T0 × 100 %) 002aab292 tf (1) (2) tr 002aab294 tsu CCLK0 CCLK1 CLK_STOP VCC VCC/2 GND VCC VCC/2 GND th |
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