AD9705-EB datasheet(36/52 Pages) AD

36 / 52 page

AD9704/AD9705/AD9706/AD9707

Rev. 0 | Page 36 of 52

Note that setting OTCM to a voltage greater than ACOM allows

the peak of the output signal to be closer to the positive supply

rail. To prevent distortion in the output signal due to limited

available headroom, the common-mode level must be chosen

such that the following expression is satisfied:

AVDD − VOTCM > 1.8 V

(10)

DIGITAL INPUTS

The AD9707, AD9706, AD9705, and AD9704 have data inputs

of 14, 12, 10, and 8 bits, respectively; and each has a clock input.

The parallel data inputs can follow standard positive binary or

twos complement coding. IOUTA produces a full-scale output

current when all data bits are at Logic 1. IOUTB produces a

complementary output with the full-scale current split between

the two outputs as a function of the input code.

DIGITAL

INPUT

DVDD

Figure 80. Equivalent Digital Input

The digital interface is implemented using an edge-triggered

master/slave latch. The DAC output updates on the rising edge

of the clock and is designed to support a clock rate as high as

175 MSPS. The clock can be operated at any duty cycle that meets

the specified latch pulsewidth. The setup and hold times can

also be varied within the clock cycle, as long as the specified

minimum times are met, although the location of these transition

edges may affect digital feedthrough and distortion performance.

Best performance is typically achieved when the input data

transitions on the falling edge of a 50% duty cycle clock.

CLOCK INPUT

A configurable clock input allows the device to be operated in

a single-ended or a differential clock mode. The mode selection

can be controlled either by the CMODE pin, if the device is in pin

mode; or through SPI Register 0x02, Bit 2 (CLKDIFF), if the SPI

is enabled. Connecting CMODE to CLKCOM selects the single-

ended clock input. In this mode, the CLK+ input is driven with

rail-to-rail swings, and the CLK− input is left floating. If CMODE

is connected to CLKVDD, the differential receiver mode is selected.

In this mode, both inputs are high impedance. Table 24 gives a

summary of clock mode control. There is no significant perform-

ance difference between the clock input modes.

Table 24. Clock Mode Selection

SPI Disabled

CMODE Pin

SPI Enabled

Clock Input Mode

CLKCOM

Single-ended

CLKVDD

Differential

In differential input mode, the clock input functions as a high

impedance differential pair. The common-mode level of the

CLK+ and CLK− inputs can vary from 0.75 V to 2.25 V, and the

differential voltage can be as low as 0.5 V p-p. This mode can be

used to drive the clock with a differential sine wave because the

high gain bandwidth of the differential inputs converts the sine

wave into a single-ended square wave internally.

DAC TIMING

Input Clock and Data Timing Relationship

Dynamic performance in a DAC is dependent on the relation-

ship between the position of the clock edges and the time at

which the input data changes. The AD970x is rising-edge

triggered and so exhibits dynamic performance sensitivity when

the data transition is close to this edge. In general, the goal

when applying the AD970x is to make the data transition close

to the falling clock edge. This becomes more important as the

sample rate increases. Figure 81 shows the relationship of SFDR

to clock placement with different sample rates.

–4

–3

–2

–1

DATA EDGE WITH RESPECT TO RISING CLOCK EDGE (ns)

80MSPS

125MSPS

Figure 81. SFDR vs. Clock Placement

POWER DISSIPATION

The power dissipation, PD, of the AD970x is dependent on

several factors that include

•

The power supply voltages (AVDD, CLKVDD, and

DVDD)

•

The full-scale current output, IOUTFS

•

The update rate, fCLOCK

•

The reconstructed digital input waveform

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