AD9705-EB datasheet(31/52 Pages) AD

31 / 52 page

AD9704/AD9705/AD9706/AD9707

Rev. 0 | Page 31 of 52

R/W N1 N0 A4 A3 A2 A1 A0 D7N D6N D5N

D00

D10

D20

D30

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

CSB

SCLK

SDIO

Figure 73. Serial Register Interface Timing, MSB First Write

R/W N1 N0A4A3

A2 A1 A0

D6N D5N

D00

D10

D20

D30

D6N D5N

D00

D10

D20

D30

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

CSB

SCLK

SDIO

SDO

Figure 74. Serial Register Interface Timing, MSB First Read

A0 A1 A2 A3 A4 N0 N1 R/W D00 D10 D20

D7N

D6N

D5N

D4N

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

CSB

SCLK

SDIO

Figure 75. Serial Register Interface Timing, LSB First Write

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

CSB

SCLK

SDIO

SDO

A0 A1 A2 A3 A4 N0 N1 R/W

D10 D20

D7N

D6N

D5N

D4N

D10 D20

D7N

D6N

D5N

D4N

Figure 76. Serial Register Interface Timing, LSB First Read

INSTRUCTION BIT 6

INSTRUCTION BIT 7

CSB

SCLK

SDIO

tDS

tDH

tPWH

tPWL

tSCLK

Figure 77. Timing Diagram for SPI Register Write

tDV

tDNV

CSB

SCLK

SDIO

Figure 78. Timing Diagram for SPI Register Read

SPI REGISTER MAP

Table 14.

Name

Addr

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SPI CTL

0x00

SDIODIR

DATADIR

SWRST

LNGINS

PDN

SLEEP

CLKOFF

EXREF

DATA

0x02

DATAFMT

DCLKPOL

DESKEW

CLKDIFF

CALCLK

VERSION

0x0D

VER[3]

VER[2]

VER[1]

VER[0]

CALMEM

0x0E

CALMEM[1]

CALMEM[0]

DIVSEL[2]

DIVSEL[1]

DIVSEL[0]

MEMRDWR

0x0F

CALSTAT

CALEN

SMEMWR

SMEMRD

UNCAL

MEMADDR

0x10

MEMADDR[5]

MEMADDR[4]

MEMADDR[3]

MEMADDR[2]

MEMADDR[1]

MEMADDR[0]

MEMDATA

0x11

MEMDATA[5]

MEMDATA[4]

MEMDATA[3]

MEMDATA[2]

MEMDATA[1]

MEMDATA[0]

TRIM

0x14

CALDACFS

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