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CS4525 Datasheet(PDF) 58 Page - Cirrus Logic |
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CS4525 Datasheet(HTML) 58 Page - Cirrus Logic |
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58 / 91 page ![]() 58 DS726A1 CS4525 6.6.3 Right-Justified Data Format In Right-Justified format, data is received most significant bit first and with the least significant bit present- ed on the last SCLK before the LRCK transition and is valid on the rising edge of SCLK. For the Right- Justified format, the left channel data is presented when LRCK is high and the right channel data is pre- sented when LRCK is low. Either 16 bits per sample or 24 bits per sample are supported. Left Channel Right Channel 65432 10 98 7 15 14 13 12 11 10 65 4 3 2 1 0 98 7 15 14 13 12 11 10 SDIN LRCK SCLK Right-Justified Mode, Data Valid on Rising Edge of SCLK Bits/Sample Supported SCLK Rate(s) 16 32, 48, 64, 128 Fs 24 48, 64, 128 Fs Figure 31. Right-Justified Serial Audio Formats |
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