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CS4525 Datasheet(PDF) 23 Page - Cirrus Logic

Part # CS4525
Description  30 W Digital TV Amplifier with Integrated ADC
PDF  91 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS4525 Datasheet(HTML) 23 Page - Cirrus Logic

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DS726A1
23
CS4525
XTI SWITCHING SPECIFICATIONS
Notes:
12. See “Clock Frequency (ClkFreq[1:0])” on page 64.
SYS_CLK SWITCHING SPECIFICATIONS
Input: Logic 0 = DGND; Logic 1 = VD, SYS_CLK Output: CL =20pF.
PWM_SIGX SWITCHING SPECIFICATIONS
Parameter
Symbol
Min
Typ
Max
Unit
External Crystal Operating Frequency
ClkFreq[1:0] = ‘00’
(Note 12)
ClkFreq[1:0] = ‘01’
ClkFreq[1:0] = ‘10’
17.510
23.347
25.650
18.432
24.576
27.000
19.354
25.805
28.350
MHz
MHz
MHz
XTI Duty Cycle
45
50
55
%
Parameter
Symbol
Min
Typ
Max
Unit
External Clock Operating Frequency
ClkFreq[1:0] = ‘00’
(Note 12)
ClkFreq[1:0] = ‘01’
ClkFreq[1:0] = ‘10’
17.510
23.347
25.650
18.432
24.576
27.000
19.354
25.805
28.350
MHz
MHz
MHz
Rising Edge RST to start of SYS_CLK
tsclko
1024*tsclki
SYS_CLK Period
tsclki
37.04
---
54.25
ns
SYS_CLK Duty Cycle
45
50
55
%
SYS_CLK high time
tclkih
16.67
---
29.84
ns
SYS_CLK low time
tclkil
16.67
---
29.84
ns
Parameter
Symbol
Min
Typ
Max
Unit
PWM_SIGx Period
tpwm
2.60
-
1.18
µs
Rise Time of PWM_SIGx
tr
-2.1
-
ns
Fall Time of PWM_SIGx
tf
-1.4
-
ns
SYS_CLK
___
RST
(output)
tsclko
Figure 9. SYS_CLK Timing from Reset
PWM_SIGx
t
pwm
t
r
t
f
Figure 10. PWM_SIGX Timing



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