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Data Sheet
ATT3000 Series Field-Programmable Gate Arrays
February 1997
64
Lucent Technologies Inc.
Electrical Characteristics (continued)
Note: The EPROM requirements in this timing diagram are extremely relaxed; EPROM access time can be longer than 4000 ns. EPROM data
output has no hold time requirements.
Figure 37. Master Parallel Mode Switching Characteristics
Notes:
At powerup, VCC must rise from 2.0 V to VCC minimum in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET
low until VCC has reached 4.0 V. A very long VCC rise time of >100 ms, or a nonmonotonically rising VCC may require a >1 µs high level on
RESET
, followed by >6 µs low level on RESET and D/P after VCC has reached 4.0 V.
Configuration can be controlled by holding RESET low with or until after the INIT of all daisy-chain slave mode devices is high.
Table 27. Master Parallel Mode Switching Characteristics
Signal
Description
Symbol
Min
Max
Unit
RCLK
To Address Valid
To Data Setup
To Data Hold
RCLK High
RCLK Low
1
2
3
—
—
TRAC
TDRC
TRCD
TRCH
TRCL
0
60
0
600
4.0
200
—
—
—
—
ns
ns
ns
ns
µs
A[15:0]
D[7:0]
RCLK
CCLK
(OUTPUT)
ADDRESS FOR BYTE N + 1
ADDRESS FOR BYTE N
(OUTPUT)
DOUT
(OUTPUT)
BYTE N
D6
D7
TRAC
TDRC
TRCD
CCLK
7 CCLKs
BYTE N – 1
2
3
1
5-3128(F)
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