LPC804 datasheet(25/89 Pages) NXP

25 / 89 page

LPC804

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Product data sheet

Rev. 2.1 — 25 July 2023

25 of 87

NXP Semiconductors

LPC804

32-bit Arm Cortex-M0+ microcontroller

9.20.1 Features

• The PLU is used to create small combinatorial and/or sequential logic networks

including simple state machines.

• The PLU is comprised of an array of 26 inter-connectable, 5-input Look-up Table

(LUT) elements, and four flip-flops.

• Eight primary outputs can be selected using a multiplexer from among all of the LUT

outputs and the four flip-flops.

• An external clock to drive the four flip-flops must be applied to the PLU_CLKIN pin if a

sequential network is implemented.

• Programmable logic can be used to drive on-chip inputs/triggers through external

pin-to-pin connections.

• A tool suite is provided to facilitate programming of the PLU to implement the logic

network described in a Verilog RTL design.

Remark: PLU cannot be used to wake-up from sleep, deep-sleep, power-down, and deep

power-down modes.

9.21 Analog comparator (ACMP)

The analog comparator with selectable hysteresis can compare voltage levels on external

pins and internal voltages.

After power-up and after switching the input channels of the comparator, the output of the

voltage ladder must be allowed to settle to its stable value before it can be used as a

comparator reference input. Settling times are given in Table 27.

The analog comparator output is a movable function and is assigned to a pin through the

switch matrix. The comparator inputs and the voltage reference are enabled through the

switch matrix.

LPC804 Datasheet(PDF) 25 Page - NXP Semiconductors