SC1486AEVB datasheet(11/29 Pages) SEMTECH

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 2004 Semtech Corp.

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SC1486A

POWER MANAGEMENT

Application Information (Cont.)

Current Limit Circuit (Cont.)

latches off due to output overvoltage (see Output

Overvoltage Protection).

Power Good Output

Each controller has its own power good output. Power

good is an open-drain output and requires a pull-up

resistor. When the output voltage is 10% above or below

its set voltage, PGD gets pulled low. It is held low until

the output voltage returns to within 10% of the output

set voltage. PGD is also held low during start-up and will

not be allowed to transition high until soft start is over

(440 switching cycles) and the output reaches 90% of

its set voltage. There is a 5µs delay built into the PGD

circuitry to prevent false transitions.

Output Overvoltage Protection

When the output exceeds 10% of the its set voltage the

low-side MOSFET is latched on. It stays latched on and

the controller is latched off until reset (see below). There

is a 5µs delay built into the OV protection circuit to

prevent false transitions. An OV fault in either controller

will not cause the other one to shutdown. Note: to reset

VDDQ from any fault, VCCA1 or EN/PSV1 must be toggled.

To reset VTT from a fault, VCCA2 or REFIN must be

toggled.

Output Undervoltage Protection

When the output is 30% below its set voltage the output

is latched in a tri-stated condition. It stays latched and

the controller is latched off until reset (see below). There

is a 5µs delay built into the UV protection circuit to

prevent false transitions. An UV fault in either controller

will not cause the other one to shutdown. Note: to reset

VDDQ from any fault, VCCA1 or EN/PSV1 must be toggled.

To reset VTT from a fault, VCCA2 or REFIN must be

toggled.

POR, UVLO and Softstart

An internal power-on reset (POR) occurs when VCCA1 and

VCCA2 exceed 3V, resetting the fault latch and soft-start

counter, and preparing the PWM for switching. VCCA

undervoltage lockout (UVLO) circuitry inhibits switching

and forces the DL gate driver high until VCCA rises above

4.2V. At this time the circuit will come out of UVLO and

begin switching, and with the softstart circuit enabled,

will progressively limit the output current (by limiting the

current out of the ILIM pin) over a predetermined time

period of 440 switching cycles.

The ramp occurs in four steps:

1) 110 cycles at 25% ILIM with double minimum off-time

2) 110 cycles at 50% ILIM with normal minimum off-time

3) 110 cycles at 75% ILIM with normal minimum off-time

4) 110 cycles at 100% ILIM with normal minimum

off-time. At this point the output undervoltage and power

good circuitry is enabled.

There is 100mV of hysteresis built into the UVLO circuit

and when VCCA falls to 4.1V (nom.) the output drivers

are shut down and tristated.

MOSFET Gate Drivers

The DH and DL drivers are optimized for driving

moderate-sized high-side, and larger low-side power

MOSFETs. An adaptive dead-time circuit monitors the DL

output and prevents the high-side MOSFET from turning

on until DL is fully off (below ~1V). Conversely, it

monitors the phase node, LX, to determine the state of

the high side MOSFET, and prevents the low-side MOSFET

from turning on until DH is fully off (LX below ~1V). Be

sure there is low resistance and low inductance between

the DH and DL outputs to the gate of each MOSFET.

DDR Reference Buffer

The reference buffer is capable of driving 3mA and sinking

25µA. Since the output is class A, if additional sinking is

required an external pulldown resistor can be added.

Make sure that the ground side of this pulldown is tied

to VSSA2. As with most opamps, a small resistor is

required when driving a capacitive load. To ensure stability

use either a 10

Ω resistor in series with a 1µF capacitor

or a 100

Ω resistor in series with a 0.1µF capacitor from

REFOUT to AGND2.

Since it is possible to have as much as 10µF to 20µF of

capacitance at the memory socket or on-board the

DIMMs, it is recommended that a 0

Ω resistor is placed

between REFOUT and the DIMM sockets. This allows the

addition of extra resistance between REFOUT and the

DIMMs to avoid spurious OVP at startup, which can occur

if REFOUT rises really slowly and VTT overshoots it. The

extra resistance allows REFOUT to rise faster, avoiding

this issue.

REFIN should also be filtered so that VDDQ ripple does

not appear at the REFIN pin. If a resistor divider is used

to create REFIN from VDDQ, then a 0.1µF capacitor from

REFIN to VSSA2 will provide adequate filtering.

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