UPD17015 datasheet(95/122 Pages) RENESAS

95 / 122 page

µPD17015

15.2.1

Power-On Reset at CPU Operation

Fig. 15-3 (a) shows power-on reset at normal operation.

As shown in Fig. 15-3 (a), when the VDD drops below 1.8 V (TA = –10 to +50

°C), the power-on clear signal is output

and operation of the device stops regardless of the input level of the CE pin.

When VDD then rises to 1.8 V or greater, after a 125 ms halt, the program starts from address 0000H.

CPU operation refers to the state in which the clock-stop instruction is not used. The power-on clear voltage in

the halt state set by the halt instruction is also 1.8 V like CPU operation.

15.2.2

Power-On Reset in Clock-Stop State

Fig. 15-3 (b) shows power-on reset in the clock-stop state.

As shown in Fig. 15-3 (b), when VDD drops below 1.8 V (TA = –10 to +50

°C), the power-on clear signal is output

and device operation stops.

However, since the device is in the clock-stop state, its operation apparently does not change.

When VDD rises to 1.8 V or greater, after a 125 ms halt, the program starts from address 0000H.

15.2.3

Power-On Reset When VDD Rises From 0 V

Fig. 15-3 (c) shows power-on reset when VDD rises from 0 V.

As shown in Fig. 15-3 (c), the power-on clear signal is being output while VDD is rising from 0 V to 1.8 V

(TA = –10 to +50

°C).

When VDD rises above the power-on clear voltage, the crystal oscillation circuit starts and after a 125 ms halt, the

program starts from address 0000H.

UPD17015 Datasheet(PDF) 95 Page - Renesas Technology Corp