UPD17015 datasheet(21/122 Pages) RENESAS

21 / 122 page

µPD17015

4.2.2

Data Buffer (DBF)

A data buffer, allocated at addresses 0CH-0FH, transfers data to and from peripheral hardware.

With the

µPD17015, the data buffer transfers data to and from the PLL data register (peripheral address 41H) when

the data (16 bits) of the PLL frequency division ratio is set or read.

See Chapter 8 for details.

4.2.3

General-Purpose Register (GR)

With the

µPD17015, the general-purpose register cannot be moved because it is fixed to low address 0 of data

memory (i.e., addresses 00H to 0FH).

The general-purpose register can be used to perform an operation on data, or transfer data to and from the data

memory, by means of a single instruction.

The general-purpose register, like other data memory, can be controlled by issuing data memory manipulation

instructions.

For details, see Chapter 6.

4.2.4

LCD Segment Data Register (LCD Segment Register)

The LCD segment register, allocated at addresses 61H to 69H, sets the display data for the LCD controller/driver.

For details, see Chapter 13.

4.2.5

Port Data Register (Port Register)

The port register, allocated at addresses 70H to 73H, sets the output data for each general-purpose port and reads

the input port data.

For details, see Chapter 9.

4.2.6

Peripheral Control Register

The peripheral control register, allocated at addresses 6AH to 6FH, sets the condition of the peripheral hardware

(such as PLL or timer).

4.2.7

General-Purpose Data Memory

The general-purpose data memory consists of data memory other than the system register, LCD segment register,

port register, and peripheral control register.

For the

µPD17015, 97 nibbles (97 × 4 bits: addresses 00H to 60H) can be used as general-purpose data memory.

UPD17015 Datasheet(PDF) 21 Page - Renesas Technology Corp