UPD17015 datasheet(96/122 Pages) RENESAS

96 / 122 page

µPD17015

Fig. 15-3 Power-On Reset and VDD (TA = –10 to +50

°C)

(a) During CPU operation (also in the halt state)

3.0 V

0 V

Normal operation

Device operation

stopped

XOUT

VDD

Power-on

clear signal

Power-on clear release

Oscillation start

Power-on reset

Program starts from address 0

Halt state

125 ms

Power-on clear voltage

1.8 V

(b) At clock-stop

3.0 V

0 V

Clock-stop

Device operation

stopped

XOUT

VDD

Power-on

clear signal

Power-on clear release

Oscillation start

Power-on reset

Program starts from address 0

Halt state

125 ms

1.8 V

Power-on clear voltage

STOP s instruction

Normal operation

3.0 V

0 V

Device operation stopped

XOUT

VDD

Power-on

clear signal

Power-on clear release

Oscillation start

Power-on reset

Program starts from address 0

Halt state

125 ms

1.8 V

Power-on clear voltage

UPD17015 Datasheet(PDF) 96 Page - Renesas Technology Corp

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