UPD17708 datasheet(323/358 Pages) RENESAS

323 / 358 page

321

µPD17704, 17705, 17707, 17708, 17709

21.6 WDT&SP Reset

WDT&SP reset includes the following:

•

Watchdog timer reset

•

Stack pointer overflow/underflow reset

Figure 21-11. Outline of WDT&SP Reset

21.6.1 Watchdog timer reset

The watchdog timer is a circuit that generates a reset signal when the execution sequence of the program is

abnormal (hung-up).

Hanging-up means that the program jumps to an unexpected routine due to external noise, entering a specific

infinite loop and causing the system to be deadlocked. By using the watchdog timer, the program can be restored

from this hang-up status because a reset signal is generated from the watchdog timer at fixed time intervals and

program execution is started from address 0.

The watchdog timer does not function in the clock stop mode and halt mode.

Resetting by the watchdog timer initializes all the registers except the stack overflow selection register, watchdog

timer counter reset register, basic timer 0 carry register, and CE reset timer carry counter.

The watchdog timer reset is detected by the WDTCY flag (R&Reset).

Instruction

count clock

65536

instruction

counter

131072

instruction

counter

Stack overflow/under

flow reset detection

circuit

WDTRES

ASPRES flag

ISPRES flag

WDTCK1 flag

WDTCK0 falg

WDTCY flag

WDT&SP

reset signal

UPD17708 Datasheet(PDF) 323 Page - Renesas Technology Corp