UPD17708 datasheet(321/358 Pages) RENESAS

321 / 358 page

319

µPD17704, 17705, 17707, 17708, 17709

(2) Releasing from clock stop status

If the device is released from the backup status when supply voltage VDD is backed up at 2.2 V by using the

clock stop status, VDD must be raised to 3.5 V or more within tSET/2 after the clock stop status has been released

by INT pin interrupt or high level input to port 0D.

As shown in Figure 21-9, the device is released from the clock stop status by means of CE reset. However,

because the power-ON clear voltage is changed to 3.5 V tSET/2 after the clock stop status has been released,

power-ON reset is effected unless VDD is 3.5 V or higher.

The same applies when VDD is raised.

Figure 21-9. Releasing from Clock Stop Status

P0D

BTM0CY flag

setting pulse

XOUT

5 V

3.5 V

2.2 V

0 V

Power-ON

clear signal

Power-ON

clear voltage

Backup in clock stop

status

Halt status

tSET/2

Power-ON clear voltage changes

to 3.5 V at this point.

Therefore, VDD must be 3.5 V

or higher before this point.

Normal operation

Backup

STOP s instruction

VDD

Program starts

Power-ON clear voltage changes

to 2.2 V at this point.

Therefore, VDD must be 3.5 V

or higher before this point.

tSET: basic timer 0 setting time

UPD17708 Datasheet(PDF) 321 Page - Renesas Technology Corp