UPD17708 datasheet(329/358 Pages) RENESAS

329 / 358 page

327

µPD17704, 17705, 17707, 17708, 17709

21.7 Power Failure Detection

Power failure detection is used to identify whether the device has been reset by application of supply voltage VDD,

RESET pin, or CE pin.

Because the contents of the data memory and output ports are “undefined” on power application, these contents

are initialized by using power failure detection.

Power failure detection can be performed in two ways: by detecting the BTM0CY flag and the contents of the data

memory (RAM judgment).

21.7.1 and 21.7.2 describe the power failure detection circuit and power failure detection by using the BTM0CY

flag.

21.7.3 and 21.7.4 describe power failure detection by RAM judgment method.

Figure 21-16. Power Failure Detection Flowchart

Program starts

Power failure

detection

Not power failure

Power failure

Initializes data

memory and output

ports

21.7.1 Power failure detection circuit

The power failure detection circuit consists of a voltage detection circuit, and basic timer 0 carry disable flip-flop

that is set by the output (power-ON clear signal) of the voltage detection circuit, and timer carry, as shown in Figure

21-1.

The basic timer 0 carry disable FF is set to 1 by the power-ON clear signal, and is reset to 0 when an instruction

that reads the BTM0CY flag is executed.

When the basic timer 0 carry disable FF is set to 1, the BTM0CY flag is not set to 1.

If the power-ON clear signal is output (at power-ON reset), the program starts with the BTM0CY flag reset. After

that, the BTM0CY flag is disabled from being set until an instruction that reads the flag is executed.

Once the instruction that reads this flag has been executed, the BTM0CY flag is set each time the basic timer 0

carry FF setting pulse rises. Therefore, by detecting the content of the BTM0CY flag when the device is reset, whether

the device has been reset by power-ON reset (power failure) or CE reset (not power failure) can be identified. That

is, the device has been reset by power-ON reset if the BTM0CY flag has been reset to 0. It has been reset by CE

reset if the flag has been set to 1.

Because the voltage at which a power failure can be detected is the same as that at which power-ON reset is

executed, VDD = 3.5 V during crystal oscillation and VDD = 2.2 V in the clock stop status.

The operation of the BTM0CY flag is the same regardless of whether the device has been reset by the RESET

pin or by power-ON reset.

UPD17708 Datasheet(PDF) 329 Page - Renesas Technology Corp