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UPD17708 Datasheet(PDF) 115 Page - Renesas Technology Corp |
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UPD17708 Datasheet(HTML) 115 Page - Renesas Technology Corp |
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115 / 358 page  113 µPD17704, 17705, 17707, 17708, 17709 11.3 General-Purpose Input Port (P0D, P1A, P1C) 11.3.1 Configuration of input port The following paragraphs (1) and (2) show the configuration of the input port. (1) P0D (P0D3, P0D2, P0D1, P0D0) Note This is an internal signal output on execution of the clock stop instruction, and its circuit is designed not to increase the current consumption due to noise even if the pin is floated. (2) P1A (P1A3, P1A2, P1A1, P1A0) P1C (P1C3, P1C2, P1C1, P1C0) Note This is an internal signal output on execution of the clock stop instruction, and its circuit is designed not to increase the current consumption due to noise even if the pin is floated. (Except P1A3, P1A2, P1A0) VDD Write instruction Read instruction Port register (1 bit) CKSTOP Note P0DPLD flag High-ON resistance Input latch To A/D converter VDD To frequency counter or A/D converter Write instruction Read instruction Port register (1 bit) CKSTOP Note |
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