UPD17708 datasheet(140/358 Pages) RENESAS

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µPD17704, 17705, 17707, 17708, 17709

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12.6 Accepting Interrupt

12.6.1 Accepting interrupt and priority

The following operations are performed before an interrupt is accepted.

(1) Each peripheral hardware unit outputs an interrupt request signal to the corresponding interrupt request

block if a given interrupt condition (for example, input of the falling signal to the INT0 pin) is satisfied.

(2) When each interrupt request block accepts an interrupt request signal from the corresponding peripheral

hardware unit, it sets the corresponding interrupt request flag (for example, IRQ0 flag if it is the INT0 pin

that has issued the interrupt request) to “1”.

(3) The interrupt enable flag corresponding to each interrupt request flag (for example, IP0 flag if the interrupt

request flag is IRQ0) is set to “1” when each interrupt request flag is set to “1”, and each interrupt request

block outputs “1”.

(4) The signal output by the interrupt request block is ORed with the output of the interrupt enable flip-flop,

and an interrupt accept signal is output.

This interrupt enable flip-flop is set to “1” by the EI instruction, and reset to “0” by the DI instruction.

If “1” is output by each interrupt request processing block while the interrupt enable flip-flop is set to “1”,

the interrupt is accepted.

As shown in Figure 12-1, the output of the interrupt enable flip-flop is input to each interrupt request block

via an AND circuit when an interrupt is accepted.

The signal input to each interrupt request block causes the interrupt request flag corresponding to each

interrupt request flag to be reset to “0” and the vector address corresponding to each interrupt to be output.

If the interrupt request block outputs “1” at this time, the interrupt accept signal is not transferred to the next

stage. If two or more interrupt requests are issued at the same time, therefore, the interrupts are accepted

according to the priority shown in Table 12-2.

Unless the interrupt request enable flag is set to “1”, the corresponding interrupt is not accepted.

Therefore, by resetting the interrupt enable flag to “0”, the interrupt with a high hardware priority can be

disabled.

Table 12-2. Interrupt Priority

Interrupt Source

Priority

Falling edge of CE pin

INT0 pin

INT1 pin

INT2 pin

INT3 pin

INT4 pin

Timer 0

Timer 1

Timer 2

Timer 3

Serial interface 0

Serial interface 1

UPD17708 Datasheet(PDF) 140 Page - Renesas Technology Corp

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