UPD17708 datasheet(141/358 Pages) RENESAS

141 / 358 page

139

µPD17704, 17705, 17707, 17708, 17709

12.6.2 Timing chart when interrupt is accepted

The timing charts in Figure 12-19 illustrate the operations performed when an interrupt or interrupts are

accepted.

Figure 12-19 (1) is the timing chart when one interrupt is accepted.

(a) in (1) is the timing chart where the interrupt request flag is set to “1” after all the others, and (b) is the

timing chart where the interrupt enable flag is set to “1” after all the others.

In either case, the interrupt is accepted when the interrupt request flag, interrupt enable-flip flop, and interrupt

enable flag all have been set to “1”.

If the flag or flip-flop that has been set last is set in the first instruction cycle of the “MOVT DBF, @AR”

instruction or by an instruction that satisfies a given skip condition, the interrupt is accepted in the second

instruction cycle of the “MOVT DBF, @AR” instruction or after the instruction that is skipped (this instruction

is treated as NOP) has been executed.

The interrupt enable flip-flop is set in the instruction cycle next to that in which the EI instruction is executed.

Therefore, the interrupt is accepted after the instruction next to the EI instruction has been executed even

when the interrupt request flag is set in the execution cycle of the EI instruction.

(2) in Figure 12-19 is the timing chart where two or more interrupts are used.

When two or more interrupts are used, the interrupts are accepted according to the hardware priority if all

the interrupt enable flags are set. However, the hardware priority can be changed by setting the interrupt enable

flags by the program.

“Instruction cycle” shown in Figure 12-19 is a special cycle in which the interrupt request flag is reset, a vector

address is specified, and the contents of the program counter are saved after an interrupt has been accepted.

It takes 1.78

µs, which is equivalent to one instruction execution time, to be completed.

For details, refer to 12.7 Operation after Interrupt Has Been Accepted.

UPD17708 Datasheet(PDF) 141 Page - Renesas Technology Corp