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UPD17708 Datasheet(PDF) 196 Page - Renesas Technology Corp |
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UPD17708 Datasheet(HTML) 196 Page - Renesas Technology Corp |
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196 / 358 page  µPD17704, 17705, 17707, 17708, 17709 194 14.2 Input Selection Block Figure 14-2 shows the configuration of the input selection block. The input selection block selects a pin to be used by using the ADCCH2 through ADCCH0 flags. Only one pin can be used for the A/D converter. When one of the P0D0/AD0 through P0D3/AD3, P1C2/AD4, and P1C3/ AD5 pins is selected, the other five pins are forcibly set in the input port mode. The P0D0/AD0 through P0D3/AD3 pins can be connected to a pull-down resistor if so specified by the P0DPL0 through P0DPLD3 flags. To use the P0D0/AD0 through P0D3/AD3 pins for the A/D converter, therefore, disconnect their pull-down resistors to correctly detect an external input analog voltage. Figure 14-3 shows the configuration of the A/D converter channel selection register. Figure 14-2. Configuration of Input Selection Block P1C3/AD5 P1C2/AD4 P0D3/AD3 P0D2/AD2 P0D1/AD1 P0D0/AD0 Selector Each I/O port ADCCH2 ADCCH1 ADCCH0 Compare block VADCIN |
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