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UPD17708 Datasheet(PDF) 240 Page - Renesas Technology Corp |
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UPD17708 Datasheet(HTML) 240 Page - Renesas Technology Corp |
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240 / 358 page ![]() 238 µPD17704, 17705, 17707, 17708, 17709 Figure 16-15. Shift Clock Generation Timing in Serial I/O Mode (1/4) Wait period 1/fSC Shift clock Wait released Initialization 1 : 1 (b) When wait operation is performed <1> If wait status is set under condition specified by SIO0WRQ0 and SIO0WRQ1 flags (normal operation) Figure 16-15. Shift Clock Generation Timing in Serial I/O Mode (2/4) Shift clock Wait released status Wait period 1/fSC Wait released Wait by SIO0WRQ1 and SIO0WRQ0 <2> If forced wait is set in wait status Figure 16-15. Shift Clock Generation Timing in Serial I/O Mode (3/4) Shift clock Wait period Wait period Forced wait set by SIO0NWT |
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